Silicon contends with stuffed and shrinking packages
By Brian Dipert, Technical Editor - June 13, 2002
(Please note: The end of this PDF includes two additional and Web-exclusive pieces of artwork that do not appear in EDN's print version.)
"More complex" and "smaller" are two common requests that system designers ask of chip vendors, often in the same breath. In the very next breath, invariably, they ask the vendors for devices that are ever faster, lower power, and lower priced, too. Packaging breakthroughs are key to enabling vendors to continually meet or exceed your seemingly divergent needs.
Looking first at the big picture, you can group the primary functions of a chip's package into three main categories:
the traffic cop, which routes power, ground, and other inputs to the die or dice and routes die or dice outputs to the rest of the system as quickly and with as little added distortion as possible;
the firefighter, which draws performance-sapping and reliability-limiting heat away from the die or dice to be absorbed by the surrounding environment; and
the soldier, which protects the die or dice from mechanical stresses and other environmental effects, while creating no stresses of its own.
Innovations in packaging technology often receive less publicity than advancements in the silicon inside them. But evolutionary and revolutionary packaging achievements are, if anything, more impressive than the now-predictable Moore's Law trends. We live in an era in which many analysts are forecasting that packaging costs will soon dominate the total cost of both low- and high-end ICs (Figure 1). As a result, adequate packaging research and development, and the breakthroughs resulting from that investment are critical to continued industry advancement.
How can you and your semiconductor suppliers work together to resolve your multifunction and multiproduct needs? The traditional scenario involves multiple suppliers delivering multiple chips, each in the smallest package possible, which you then attach to and interconnect on the system board. On the other end of the spectrum is the highly hyped system on chip, which combines all necessary functions on a single piece of silicon. Between these two extremes is the multichip module, combining several unpackaged die or already-packaged devices in a horizontal miniature pc board or vertical stack under a common package lid. These options all have trade-offs. Engineers have different system needs and priorities, and they invariably come to different conclusions about which option is best for them.
Legs and bumps
Leaded (legged) packages, such as DIPs, PLCCs, SOPs, and QFPs represent the lion's share of all packages used today. Also known as "boundary" packages (a category that also includes leadless packages), their connections to the outside world align along one or multiple edges of the package, and they come in both through-hole and surface-mount connection options. Surface-mount packages are becoming increasingly popular, except possibly in prototyping environments, in which easy replacement of chips is desirable, and in manufacturing environments that value the just-in-time insertion of a chip before shipping the system to a customer. Sockets are options in these cases. However, they increase system cost, and their added impedance may negatively affect performance and signal integrity.
Speaking of impedance, it's one reason, though not the primary one, that array-packaging contenders, such as BGAs and PGAs are rapidly growing in popularity (Figure 2). Ball, or bump, connections offer lower impedance than leads. More important, as device pin counts increase, array packages usually offer more space-efficient board footprints than do boundary packages.
The "usually" qualifier is important for several reasons. It's common today to find QFPs with lead-to-lead spacing, or pitch, measuring 0.05 mm, because it's often unnecessary to route signal traces between the QFP leads. Instead, you can bring signals to the top of the board using vias within the bare cavity that the pinout boundary defines and then fan out the signals to the leads. Conversely, most array packages have no cavity; some have a small one. Regardless, you almost always need to route traces between bumps to reach the interior of the array. As the array grows, the number of signals to route increases. Fine-pitch traces, multilayer boards, and buried vias all significantly increase board cost.
Today's high-pin-count chips, therefore, rarely employ bump pitches less than 1.2 or 1 mm. Lower-pin-count and, therefore, smaller-array parts, such as flash memories, might use a 0.8-mm pitch, and you can find even 0.5-mm pitch packages for use in extremely space-sensitive applications. Low-impedance BGA sockets, often employing elastomeric connections, come from companies such as Ironwood Electronics. As an alternative to BGAs, companies such as Advanced Interconnect Technologies are advocating next-generation boundary packages, such as the no-lead VFQFP and thinner WFQFP. The company claims that these packages deliver BGA-like board footprint areas for all but the highest pin counts and much lower impedance than do traditional leaded packages. VFQFP and WFQFP come in both wire-bonded (Figure 3) and flip-chip-based versions.
The PGA is the odd man out in the boundary-versus-array packaging debate. Like a through-hole boundary package, you can easily socket it. (This feature is important in situations in which, for example, a PC manufacturer wants to support numerous processors and, therefore, system-performance speeds with a single board design.) Like array packages, PGAs are board-space-efficient. They ship in huge volumes, driven by PCs, but, due to their costly requirement for either a socket or a fine-pitch through-hole pc board, they're largely unpopular outside that application.
The terminology you encounter in investigating array packages might confuse you. Specifically, the acronyms BGA and CSP often seem to refer to packages that look identical. Historically, a CSP was a package that, using common industry conventions, was no more than 20% larger than the die it housed. BGA technology advancements over the past few years have made this 20% rule the norm rather than the exception, so more and more people are using the two acronyms interchangeably.
Given the increasingly svelte array and boundary packages now housing die, what place do bare die have in the packaging smorgasbord? In the past, manufacturers used them in the most space-constrained applications, and they are still key ingredients in multidie chips. But they're difficult to handle in a manufacturing environment. The required bond wires or balls and the encapsulating overmold increase system cost and negate subsequent board-rework capability. And, suppliers' abilities to test bare die for speed and reliability are limited.
Looking under the lid
Package alternatives may look similar from the outside. Dissect them, though, and their differences become more apparent. Two primary factors—heat dissipation and signal integrity—determine the orientation of the die relative to the substrate and the interconnection between the die and substrate. Looking first at the conventional BGA or CSP, you see that the material lying between the die and the outside world is the overmolding of ceramic or plastic (Figure 4a). You also notice that bond wires interconnect the die and the substrate. A bond-wire variant, TAB (tape-automated bonding), patterns the die-to-leadframe interconnections on a multilayer polymer tape.
Now, compare the conventional BGA with a cavity-down BGA (Figure 4b). The die-to-substrate interconnect scheme is still the bond wire. But, with the die now mounted upside-down, the vendor can directly attach a metallic heat spreader or heat sink to its backside.
Finally, take a look at the flip-chip BGA (Figure 4c). Again, the die is upside-down for direct attachment of a heat spreader. But this time, the interconnection between die and substrate consists of bumps, not bond wires. Why? Perhaps this estimate from Vincent Wang, PhD, Altera's senior director of packaging, will provide a clue. Wang estimates that, whereas the typical bond wire has an inductance of 4 nH, a flip-chip bump's inductance is 0.4 nH. Reduced inductance means reduced signal distortion and increased propagation speed, along with rock-solid power and ground connections and robust heat transfer away from the die. And chip designers can put bump connections in optimal die locations, instead of, by necessity, placing them all on the die boundary. Intel, for example, has converted nearly 100% of its PC-microprocessor production to flip-chip-packaged devices.
Higher performance, alas, doesn't come for free. The bump-attachment process increases die cost. The required ultrafine bump-contact pitch has significantly higher package-substrate cost than a bond-wire-mated alternative (see sidebar "Future fashions"). And, for added stability, the gaps in the matrix between bumps become filled with an undermold material that hardens under microwave exposure, adding more cost. For these reasons, Altera's Stratix FPGAs will come in a mix of packages: bond-wire-based for low cost in low-chip-speed bins and flip-chip-based for the fastest, most expensive chip-speed bins. Note that bond-wire and flip-chip interconnection options are generic to both array and boundary packaging.
Another key function of the undermold is to buffer the differing coefficient of expansion and contraction (tCE) of the die and the substrate. Bond wires also act as mismatch buffers. Tessera's µBGA package dispenses with the substrate, relying instead on a flexible elastomer material. The downside of Tessera's approach, though, is that it's closely tailored to the die size and layout; a chip redesign or process-lithography shrink invariably forces changes in the package dimensions, along with the bump-matrix pinout and pitch. More conventional substrates, which you can conceptually think of as mini pc boards, hide these die-level changes from the outside world.
Mismatches in tCE between the substrate and the system pc board also require careful consideration. One of the factors driving the switch to organic substrate materials is that their tCE has closer equivalence to FR4 and other common pc-board raw materials. When considering temperature effects, keep in mind that both the absolute minimum and maximum temperatures and the rate of temperature cycling between those extremes are important. The system can experience rapid temperature changes during both normal operation and manufacturing (during wave soldering, for example).
And, speaking of wave soldering, it's a common environment to experience another critical packaging-failure mechanism, this one related to moisture. Have you ever wondered why chips come with stringent specifications on how long you can keep them out of their desiccant packaging before soldering them to the board for or how long you need to bake them before soldering if you've exceeded this time threshold? Packages absorb atmospheric moisture; think of them as miniature sponges. Subject them to extreme heat, and, if they contain more moisture than can escape as steam, they'll pop right off the board—a phenomenon not surprisingly known as "popcorning."
Hungry for a short stack?
Some systems are so space-constrained that simply shrinking the footprint and height of each chip's package is insufficient. At this point, you need to consider combo packaging, which unites multiple die or already-packaged chips under a common encapsulation. Or, more pragmatically, an MCM (multichip module) may be appealing to you, simply because it reduces the number of chip vendors from which you need to obtain products.
The MCM concept has been in use for a long time; IBM mainframes several decades ago employed TCM (thermal-conduction-module) packaging. Until recently, however, its high cost has limited its widespread adoption. Even today, potential chip-cost savings should not be a primary reason to consider an MCM, although companies such as Sharp claim that they've perfected the MCM manufacturing process to the point of near cost parity with the bag-of-chips alternative.
System-cost savings are possible, however. By shifting some of the chip-to-chip interconnect away from the system pc board and onto the package, you might be able to reduce the complexity and cost of the system pc board. And, as cellular-phone manufacturers have discovered, even if a stacked flash-memory-plus-SRAM MCM is more expensive than a two-chip substitute, you can sometimes more than make up the difference by charging a higher price for the much smaller resultant system.
MCMs' biggest success story to date has come with advanced cellular phones, in the form of a linear (DiNOR, NOR) flash-memory-plus-SRAM combo (see sidebar "Standards shortfall and a subsystem perspective"). As the required amounts of code-, data-, and file-storage memory increase with the phone's transformation into a multifunction device, manufacturers are adding serial flash memory (AND, NAND) and DRAM to the mix, resulting in three- and four-die chips. Fujitsu claims that it can even provide eight-die stacks for specialty applications. Between-die spacers resolve differences in die size and orientation.
Ordering an MCM might be a simple matter for you, but it's an integration headache for your supplier, especially if it doesn't manufacture all of the dice inside the package. First off, to avoid creating an unacceptably tall package, the manufacturer must back-grind each die to reduce its thickness. It's also difficult to impossible to fully test a device in bare-die form; speed is a function not only of the die itself but also of the package interconnect and lead frame, and infant-mortality testing to screen out latent silicon-oxide defects must occur at high temperatures (a process called "burn-in"). Burning in an MCM to test one die might adversely affect another die in the module. And if one of the die in an MCM fails testing, the manufacturer ends up with a much more expensive paperweight than with a traditional single-die-packaged part.
If the vendor creating the MCM lacks in-house expertise in testing a given die (such as with a flash-memory supplier that obtains SRAM from other companies), procuring sufficient ongoing process and product knowledge to ensure adequate testing coverage can be a legal and logistical negotiation nightmare. Dice from different manufacturers have different dimensions and require requisite packaging adjustments. And every time a manufacturer redesigns one of those die, package readjustments are also necessary. MCM strategies to reduce discards include employing dice manufactured on trailing-edge processes (where oxide defects are well- understood and minimized) and not pushing speed (to maximize ac-testing yield).
Fortunately, all of the vendors this article covers claim that multimemory MCMs have no thermal issues that might prevent you from, for example, reading from the SRAM while programming or erasing the flash memory. Thermal concerns become more significant, however, when you consider a logic-plus-memory MCM. Sharp, for example, currently ships multidie combinations of its BlueStreak ARM-based CPU and various memories, both to its internal systems divisions (think camcorders and PDAs) and to key external customers.
In the past, notebook-computer manufacturers ensured graphics-subsystem memory and manufacturer flexibility by employing an AGP- or PCI-connector-based graphics minimodule. Today's thin and light computers have insufficient room for such modules, though. Nowadays, mobile graphics accelerators from companies such as ATI Technologies and Nvidia commonly combine logic and DRAM chips within a single MCM. Historically, graphics suppliers used bare die, but to ensure more complete test coverage, they're now integrating partners' BGA-packaged memories. Partially to circumvent heat concerns, these companies horizontally orient the multiple chips inside the MCM, although Nvidia combines four memory chips and a graphics die in a pseudovertical-stack arrangement. A horizontal orientation, however, doesn't save board space, and lack of board space is often a primary motivator for an MCM in the first place.
More generally, logic-plus-memory MCMs tend to use lower voltage and slower and, therefore, less-heat-generating, logic than you would commonly find use in discrete chips. One other testing issue that affects your system-board-manufacturing throughput is whether you can independently access multiple dice inside the MCM (and thereby be able to test them in parallel) or whether you need to access one or several of the die "through" another die, resulting in a slower serial-testing sequence.
|Other companies mentioned in this article|
Advanced Micro Devices (AMD)
Institute of of Electrical and Electronics Engineers (IEEE)
Joint Electron Device Engineering Council (JEDEC)
|I'm especially grateful to Vincent Wang, PhD, Altera's senior director of packaging, for identifying and explaining packaging trends within both his company and the industry at large.|