µC-based circuit performs frequency multiplication
Yongping Xia, Teldata Inc, Los Angeles, CA - May 27, 1999
The traditional frequency multiplier requires many elements: a phase comparator to detect the phase error between the input and the output signals, a lowpass filter to convert the phase error to a dc control signal, a VCO to generate the output, and a divider to set up the multiple ratio. The circuit in Figure 1 uses a different approach to multiply frequency with a programmable multiple ratio from 1 to 7 (Table 1). Because the circuit is edge-triggered, the 50% output duty cycle is independent of the duty cycle of the input waveform. Test results show that the output frequency-range is from 31 Hz to greater than 30 kHz.
The AT90S1200 is a low-cost, high-speed µC, and most instructions need only one clock cycle. With a 12-MHz clock, these instructions take 83.3 nsec. This number places the high limit on the input frequency because software performs all functions. The program in Listing 1 includes an endless loop to generate a square-wave output. The frequency of the output depends on the value of a 16-bit delay register that comprises two 8-bit registers: dly_1 and dly_2. The delay function is a countdown loop until it reaches zero. The larger the number in the delay register, the longer the delay time. The functions of the endless loop and the delay register are analogous to a VCO.
The AT90S1200 has an 8-bit counter whose input is the output signal. Because this counter is an up counter, the programmable multiple ratio loads into the counter in the 2's complement format. For instance, if the multiply ratio is four, the software loads that counter with 0xfc. Because the initial value of the counter is 0xfc, four output pulses cause the counter to overflow, which generates an interrupt. The function of this counter is analogous to the divider in a traditional frequency multiplier.
Every rising edge of the input signal also generates an interrupt. Thus, the interrupt subroutine must identify the events that trigger the interrupts. If the input causes the interrupt, the frequency of the output is too low. If the counter triggers the interrupt, the output frequency is too high. In both situations, the software must adjust the value of the delay register accordingly. The interruption subroutine is analogous to a phase comparator.
Table 1—Frequency-multiplier settings