EDA tools pave path to 3-D ICs, part 1
Mike Demler, Technical Editor - June 9, 2011
A recent article (Reference 1) posed three questions regarding 3-D ICs: What are 3-D ICs, are they real, and what difference do they make? The answers to these questions may vary, but the semiconductor industry is increasingly adding a vertical—that is, stacked—alternative to traditional 2-D Moore’s Law scaling (Reference 2).
Reducing the length of interconnects between ICs can make a big difference in performance, power, and package size in mobile-system applications—major drivers for 3-D ICs. Combining a mobile-processor die with a separate memory chip is a natural development for a 3-D structure. For example, Samsung Electronics recently introduced a 3-D IC, which the company stacks with a memory chip that connects using TSVs (through-silicon vias)—vertical, metallized holes in the silicon die that create connections on both the top and the bottom of a chip (Figure 1). TSV technology enables a wide I/O-memory interface, reducing power by as much as 75% versus other approaches as a result of the lower load capacitance of interconnect and I/O circuits.
Tezzaron Semiconductor, which specializes in memory products, 3-D-wafer processes, and TSV processes, stacks chips in three layers by using a wafer-bonding technique that employs copper supercontacts similar to the method the US Mint uses to make quarters in a copper-nickel-clad process. Tezzaron’s Super-8051 microcontroller with stacked memory consumes 90% less power than a typical 8051 microcontroller because it has no off-chip I/O. It does not, however, allow manufacturers to probe wafers before bonding because probe marks can cause defects.
To mitigate some of the challenges of 3-D stacked ICs, many companies are taking an intermediate step—2.5-D—to connect dice with a passive silicon interposer (Figure 2). Many industry participants, including Mentor Graphics Chief Executive Officer Walden Rhines, see the 2.5-D approach as providing a long transitional ramp to 3-D ICs (Reference 3). Rhines believes that 2.5-D approaches will be around longer than many people expect because the approach is more evolutionary than revolutionary.Xilinx has also taken this approach in its new 2.5-D SSI (stacked-silicon-interconnect) FPGAs, including the Virtex-7 XC7V2000T, which integrates four FPGA dice with the equivalent of 2 million logic cells, 46,512 kbits of block RAM, 2160 DSP slices, and 36 10.3125-Gbps Xilinx GTX (gigabit-transceiver-extension) transceivers (Figure 3). By stacking the dice on a passive silicon interposer, Xilinx enables more than 10,000 interconnects between the FPGAs. Showing again how 2.5- and 3-D make a difference in power and performance, Xilinx achieved a better-than-two-orders-of-magnitude improvement in I/O bandwidth per watt with SSI versus other approaches, says Ivo Bolsens, Xilinx’s chief technology officer.
Your choices of EDA tools to support a new 3-D-IC project can make a difference in how you approach your design. Although you may be able to adapt your current 2-D-IC tools, you might also benefit by adding some technology targeting the challenges of 3-D design. Most of the major EDA vendors are taking a cautious wait-and-see approach to 3-D ICs by gradually adding features to their 2-D tools. Meanwhile, several smaller EDA vendors are building tools focusing on 3-D design. The Tezzaron 3-D PDK (process-design kit), for example, combines new and established tools that will help you move your design method to 3-D.
The development of EDA tools for 3-D ICs must begin with TCAD (technology-computer-aided design) for modeling the physical characteristics of the TSV, according to Marco Casale-Rossi, product-marketing manager for Synopsys’ implementation platform. The company’s Silicon Engineering Group has undertaken this activity with several selected partners. Designers must address the fact that TSVs induce stress in the active silicon area near the via cut, which can potentially interfere with circuit behavior. At process geometries of 28 nm, the “keep-out zone”—the area around a TSV in which you cannot insert active circuitry—can consume an area equivalent to approximately 5000 transistors. Placing a large number of TSVs on a chip with the associated keep-out zones can result in a large amount of unusable die area, says Casale-Rossi. Synopsys recently filed for a patent for technology to address TSV-induced stress. The technology goes beyond TCAD software to IP (intellectual property), which Casale-Rossi predicts will contribute to stress-mitigation methods in 3-D-IC fabrication (Reference 4). The company has also filed patent applications for RLC (resistance/capacitance/inductance) modeling and extraction in 3-D ICs (references 5 and 6).
Synopsys bases the development of 3-D-IC physical-implementation tools on its 2-D place-and-route tools. Synopsys is developing a 2.5-D tool for designs that connect multiple flip-chips with microbumps through a silicon interposer. An emerging 3-D-IC design flow will be TSV-aware at every step of current flows—from synthesis and placement and routing to extraction, physical verification, and timing signoff for digital designs (Figure 4).
Adding floorplan levels
Because no currently available EDA tools support automated placement and routing of TSVs, you must manually add tools using existing tools for 2-D-IC design. According to Dave Noice, Cadence Fellow, modifying 2-D tools and design databases to support the concept of 3-D ICs involves many challenges. For example, in 2-D designs the first metal, or metal-1, layer represents the lowest interconnect layer on an IC, but 3-D ICs change that placement by adding backside metal to make connections through TSVs.
Designers have previously been able to use Cadence’s Encounter digital implementation tools to automatically route flip-chips, with 45° routing for bumps and I/Os. Cadence also enhanced that feature to provide support for I/O routing on both the top and the bottom of a die. After you add TSVs to a chip during the floorplanning and placement stage, the next challenge you will face is assigning connections. A routing tool must be able to assign a connection and optimize wire length through the TSVs to backside bumps. Some users mistakenly believe that a router can place the TSVs, says Noice, but designers can use routers only to make the connections. In a stacked-die configuration, designers’ flexibility constrains floorplanning—whether they are adding TSVs to a new ASIC or modifying a design for use in a 3-D package.
For 3-D-IC designs, Cadence’s floorplanning tools treat the problem as if it were a normal hierarchical 2-D design. The tools treat each die as a separate subblock. For example, if a given manufacturing process stacks memory dice, die “owners” can see the vertical-connection interface for design optimization but can make edits only on their side of the TSV stack.
Magma Design Automation is extending its Hydra floorplanning tool to automate 3-D designs by treating a 3-D chip as a set of 2-D blocks for physical implementation. According to Patrick Groeneveld, PhD, chief technologist at Magma, partitioning a 3-D design into the constituent 2-D components can give rise to a number of new issues, such as design partitioning, TSV assignment, interfaces across dies, power and ground distribution, and the associated IR drop and temperature analysis.
The market for 3-D-IC design tools has been too small to attract investment by the big EDA companies, according to Mark Mangum, sales and marketing manager at privately held EDA company Micro Magic. The company has been working on the Max-3D layout tool for the last four years, with 3-D design patents from one of its development partners (Reference 5). Conventional layout tools cannot handle the traditional approach for 2-D design—organizing all the disparate data into one huge file, says Mangum. Max-3D, in contrast, allows you to maintain technology files for each wafer level, with a separate file for the TSV interconnects (Figure 5). Engineering teams of processor and memory designers, which are common in projects for 3-D ICs, can work independently on their parts of the 3-D stack before final integration.
After assembly of the 3-D-IC database, you must verify your design by tracing the connectivity of the TSVs through the entire stack and perform complete DRC (design-rule checking) and LVS (layout-versus-schematic) checks. You must somewhat adapt the 2-D physical-verification tools, but Max-3D eases this process through its integration with Mentor Graphics’ Calibre DRC and LVS tools. Micro Magic is also working with Magma to integrate the company’s Quartz LVS and DRC tools into Max-3D. Magma’s Groeneveld says that future enhancements to Quartz will enable users to work directly with the multiple process descriptions that are necessary for 3-D ICs. With Quartz LVS, you can check each of your 2-D chips, as well as the 3-D interconnections between them, in a single run (Figure 6). You specify the number and order of layers, the interconnect material, and other physical parameters of your design in a 3-D technology file. You then perform a TSV-aware extraction of your 3-D IC’s connectivity, using the debugging environment in Quartz to analyze any LVS mismatch.
Magma intends to add 3-D-DRC features to Quartz by working with customers and manufacturers to define the rules, design, and library information that will be necessary to verify designs with TSVs. According to Groeneveld, Magma is also working on several other projects for 3-D ICs, including adding the ability for users to visualize and edit multiple dice at once in the Titan custom- IC layout editor with builtin Quartz DRC and LVS checking.
Click here to continue reading: "EDA tools pave path to 3-D ICs, part 2."
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