Latches and timing closure: a mixed bag
Latch-based designs, however, have smaller dice and are more successful in high-speed designs in which the clock frequency is in the gigahertz. In flip-flop-based high-speed designs, maintaining clock skew is a problem, but latches ease this problem. Hence, the use of flip-flops can limit the design’s performance when the slowest path limits the frequency of the design. When you consider process variation, latch-based design is dramatically more tolerant of variations than is flip-flop-based design, resulting in better yield, allowing more aggressive clocking than the equivalent design with flip-flops, or providing both of these benefits.
Using latches to borrow time
In Figure 3, data arrives from Logic A at Latch 2 before the falling edge of the clock at the latch. In this case, the behavior of the latch is similar to that of a flip-flop, and the analysis is simple. You need not borrow any time to achieve your timing goal. In Figure 4, the negative clock edge enables the latch before the arrival of the signal from Logic A at the input of the latch, so the latch enters transparent mode and for a time transmits an undefined state from Logic A through to Register B. It is important that the new state from Logic A reaches and passes through Logic B in time to meet the setup requirements of Register 2. So, if Logic B has a short propagation delay, you can, in effect, let Logic A have some of the time you reserved for Logic B, and the circuit will still work. Logic A borrows this extra time to complete its propagation delay. When Path 2 is timed, the timing analysis considers the end of the borrowed time as the starting point for analyzing Logic B’s delay.
In an ideal scenario, the time at the starting point should equal the time the latch borrows. Due to shrinking process technology, however, OCV (on-chip variation), signal-integrity, and other factors come into play. To increase the accuracy of the analysis, you can also use CPPR (common-path-pessimism-removal) techniques. These factors complicate the relationship between time-borrowing and time for the starting point. As a result, the timing analysis of latches becomes more challenging.
Applied uncertainty in Path 1 is the uncertainty for the clock path of the latch, which is not part of pessimism when the latch is transparent. You thus remove that pessimism about the latch clock’s uncertainty from the start time. Similarly, you recover pessimism due to CPPR in the time for the starting point because the same early or late path type of latch-launch clock path is in Path 2. If you want to apply clock derating in the design during the timing of Path 2, you should consider using early rather than late derating to make the path the same as the capture clock of Path 2.
You can also consider using the smallest value between the CPPR of Path 1 and that of Path 2. This approach is not the most accurate, but it provides another level of pessimism removal. Comparing the common clock path of the register and the latch in timing Path 1 versus the common clock path of the latch and the endpoint—the second register—in timing Path 2 can give an idea of the minimum possibility of the clock path between the register and the final endpoint.
Once you ensure that the latch will be transparent during path timing, the least preferred, most accurate, and best way to judge the timing of latches is to make the latch transparent by using a case analysis on the enable pin of the latch. After this step, the EDA tool can time the two segments as one complete path. This method is the least preferred because the latch may not always be transparent when timing Path 1 in the best-case condition: when time borrowing is unnecessary. The tool also misses all the paths that do not require time borrowing and holds a time check at the latch’s endpoint.
In summary, latches are beneficial for high-speed-SOC designs, but their use adds challenges in static-timing analysis, especially with hierarchical design. The limitations of EDA tools increase the complexities of latch-based design. You can employ latches in SOCs only after careful analysis. You can then apply some of these techniques, which can reduce the complexities of designing with latches.
This article originally appeared on EDN’s sister site, EDA Designline.
Ashish Goel is a lead design engineer at Freescale in India. He has 11 years of industry experience in static-timing analysis, RTL (register-transfer-level) design, physical design, and formal technologies. Previously, he worked at STMicroelectronics, Agilent Technologies, and Infineon Technologies. Goel holds multiple patents in FPGA architecture.
Ateet Mishra is a senior design engineer at Freescale in India, where he has worked for six years. He has experience in static-timing analysis, physical design, and synthesis. He has successfully taped out multiple SOCs.