Die-to-die bonding using copper pillars

In packaging applications for cellular electronics devices, the use of flip chip copper pillar bumps has been expanding due to its better shape, lesser thickness, smaller form factor, better performance and lower power consumption. Foundries and semiconductor manufacturers are actively evaluating this new technology as the chips are becoming complex and size is shrinking day by day which leads to higher pin count and large interconnect densities which can hamper manufacturability of the bump pad.

This paper provides an update on the advantages of copper pillar bumps over conventionally used solder bumps; copper pillar bump design and layout, fabrication and benefits in flip chip package assemblies.

Advantage of copper pillar bump over conventional solder bump
Flip chip technology is keeping pace with the increasing connection density of ICs and is capable of transferring semiconductor performance to the printed circuit board. The pitch is growing smaller, which means flip chip technology with solder bumps will unavoidably run up against its technical limitations. The reason for this is the spherical geometry of the bumps.

One solution to this problem is copper pillars. In this contact technology for flip chip assembly, special cylindrical copper connections function with a solder deposit instead of the usual solder ball bumps to form the connecting element between semiconductor and substrate. The result: improved reliability and enhanced electrical and thermal connection characteristics, greater connection density with narrower pitch and Restriction of Hazardous Substance (RoHS) conformity.

Copper pillars offer advantages over solder bumps such as higher interconnect densities, higher reliability, improved electrical and thermal performance, and reduction or elimination of lead. While solder bumps collapse during solder reflow, copper pillars retain their shape in the x, y, and z directions as shown in Figure 1. This allows for fabrication of finer bump pitches, smaller passivation openings, and finer redistribution wiring for higher interconnect densities.


Table 1 lists the advantages of copper pillar bumps over conventional solder bumps.

Copper pillar bump design and layout
The die to die copper pillar bump pad is used for a chip to chip connection. These pads are of the Aluminum Cap (ALUCAP) shapes that are exposed by the opening in the final passivation (mask level nitride) coincide with the copper pillar marked area. Area for the copper pillar is being marked by the marker layer (CAD Layer) that identifies the location of the bump balls. Routing redistribution can be designed in either the top metal layer available in the technology or aluminum cap layer.

Figure 2 shows the design of AP redistributed die to die copper pillar bump pad which has two sides input and output. Input side is connected to the chip side through the MTop (Top Metal Layer) and output side is connected to the outside world through AP.



For die to die copper pillar bump pad, four masks are generated from the CAD layers as shown in fig. 3 which represents the Layout of the copper pillar bump pad.

1. ALUCAP VIA provides access to MTop – PADOPEN (connection from the chip side) generated from ALUCAP VIA
2. AP defines the Aluminum pad cap – ALUCAP (connection the outside world) generated from AP
3. Nitride Passivation is the opening for bump – NITRIDE (Pillar position)
4. Marker for the pillar is coincide with Nitride passivation to connect to UBM (Under Bump Metallurgy) for the pad

Here the pillar is hex decagon (16 side polygon having uniform angel between all the sides) to provide a very close to spherical shape with edges so that it can fabricate firmly and have small and regular shape.

AP Layer (ALUCAP) is in hexagonal shape, nitride passivation coincide with marker layer for pillar is in a hex decagon shape and two APLUCAP vias are in a square shape for connection from MTop are representing in layout of copper pillar.

Copper pillar bump fabrication
The fabrication the copper pillar bump involves even essential fabrication steps including under bump mettalurgy (UBM) deposition, patterning, polymer coating, electroplating and alignment. After each individual process, an optical microscope (OM) and scanning electron microscope (SEM) were used to observe the plain view and cross section morphologies of the copper pillar.

Step was used to evaluate the uniformaties of the copper pillars either on a chip or on the entire wafer. The ratio of each element contained in the eutectic dramatically influences the final reflow temperature, so an energy dispersive spectrometer (EDS) was particularly used for analyzing the ratio of Sn and Cu after plating.

Benefits of Copper pillar in flip chip package assemblies
Copper pillar bumps usage is expanding dramatically by the semiconductor manufacturers and foundries due to its following benefits in the flip chip package assemblies:

• Low cost
• Lead free
• Available with and without wafer re-passivation
• Superior Electro migration performance
• Fully developed finite element models for optimizing chip package interactions to improve long-term reliability
• Qualified for advanced silicon node with low-k dielectrics

Conclusion
Copper pillar bump technology is a fast emerging technology for die to die bonding due to its several advantages over conventional solder bump technology. Fabrication labs and the semiconductor industry are looking torwards adapting coppar pillar bumps for deep sub micron technology chips due to its high reliability in high pin counts and high packaging density. Various innovations are going on to make copper pillar technology more stable and more cost effective.

References
1. j. Kloeser and E.Weibach, "High-Performance Flip Chip Packages with Copper Pillar Bumping" Global SMT and Packaging, May 2006
2. Tie Wang, Francisca Tung Shu et al, "Studies on A Novel Flip-Chip Interconnect Structure-Pillar Bump," Proc 51thElectronic Components and Technology Conf, Orlando, FL, May. 2001, pp. 945-949. [A reference to a presentation at a Conference…]

Authors
Deepak Sharma: Working at Freescale Semiconductors, India as Senior Design Engineer and 8 years of experience in Physical Design, Analog Layout Design and Standard Cell Library Design.

Sachin Kalra: Working at Freescale Semiconductors, India as Senior Design Engineer and 6 years of experience in Physical Design, Analog Layout Design and Standard Cell Library Design.

Azeem Hasan: Working at Freescale Semiconductors, India as Senior Design Engineer and 4 years of experience in Physical Design, Analog Layout Design and Standard Cell Library Design.

Rahul Saxena: Working at Freescale Semiconductors, India as Staff Design Engineer and 12 years of experience in Physical Design, Analog Layout Design and Standard Cell Library Design.