Is high-level synthesis ready for prime time?

After years of promises that next year would be the year of ESL (electronic system-level) design, the knee of the curve is now behind us, EDA analyst Gary Smith declared at this year’s DAC (Design Automation Conference). ESL revenue grew from $262 million in 2010 to $460 million last year, Smith noted.

But he also reported that Forte Design Systems Inc, a supplier of TLS (transaction-level synthesis—my term for HLS [high-level synthesis]), grew 30% last year. The numbers for the comparable period for CatapultC, which competes with Forte’s TLS offering, are skewed because Catapult changed hands from Mentor Graphics to Calypto Design Systems Inc last summer, and the two companies use different accounting methods. Still, TLS growth appears to lag the overall growth of the ESL segment.

Hoping to gain insight on that disparity, I attended a DAC panel titled “High-Level Synthesis Production Deployment: Are We Ready?” According to the session abstract, “High-level synthesis has historically over-promised and under-delivered, but that is all about to change. Or, is it? Are we ready to climb the ladder up to the next level of design abstraction?”

With that question as a backdrop, Clem Meas of QuickStart Consulting introduced the panelists, who represented Cadence Design Systems, Calypto, Freescale Semiconductor, Intel Corp, NEC Corp, and Xilinx Inc. It was unfortunate that vendors of TLS with a vested interested in promoting its progress dominated the panel; even NEC, which might look like a customer for the technology, is in fact a supplier. There were two clear customer voices on the panel, however: Freescale’s Mark Johnston and Intel’s Eli Singerman.

Johnston, principal EDA architect at Freescale, views TLS with skeptical optimism. Freescale has been running some pilot programs, and Johnston said those trials need to demonstrate proof of productivity gains and competitive QoR (quality of results) compared with handcrafted RTL before TLS is adopted more broadly.

One impediment to TSL adoption is the steep learning curve, Johnston said; RTL designers, who generally take one C class in college, have to let go of their familiarity with RTL and of the bit level. What’s more, coding for the tools is somewhat unintuitive; restrictions are arbitrary and are poorly documented, Johnston said. Compared with Verilog, C++, and SystemC are difficult to master and thus can be a source of designer frustration. Johnston also cited a lack of library code, along with the need for a better ECO (engineering change order) flow and low-power requirements.

Designs have grown significantly since the 20,000-transistor designs common during the Mead and Conway era. By 1994 and the dawn of the behavioral compiler, the typical design had grown to 2.5 million transistors. By 2000 and the introduction of SystemC, the transistor count had grown to 20 million. By 2008 and the release of TLM-2, the common count was 328 million. Currently, the norm is 1.3 billion transistors; by 2020, it will be 21 billion. Johnston asked whether TLS was up to the challenge.

Not yet, but it can get there, responded Singerman, an engineer with Intel’s design and technology solutions group. There is already ample proof that raising abstraction is the best way to improve productivity and that RTL is no longer sufficient, Singerman said. Intel has conducted a few TLS pilots, primarily datapath, with some control. Singerman called the results encouraging but said Intel had identified gaps that EDA and user companies must work together to fill.

Singerman cited the steep TLS learning curve for hardware designers. That complaint is a bit of a head scratcher. The touted rationale for TLS is that everyone already knows C, C++, and SystemC, and that C’s similarities to Verilog make it a natural language for bringing together the hardware and software communities. It appears we may have been sold a story.

Singerman’s next point was that SystemC, not detailed RTL, is the major verification target. The problem is that EDA offerings are subpar compared with RTL verification, he said. Intel has been forced to develop an internal solution, and it wants to see EDA step forward. Equivalence checking is available but has a long way to go, Singerman said.

Ironically, although proponents cite verification as one of the largest benefits associated with TLS, there was no verification representation on the panel.

Another obstacle is the integration of TLS results with legacy RTL, including DFX (design for X), debug hooks, and clock gating. Verification also needs to be integrated across the abstraction levels, with common stimulus, checkers, and coverage. Today, the integration efforts can offset the benefits of the flow, Singerman said.

He further complained that commercial tools have added proprietary extensions to SystemC that make it difficult for engineers to move from one tool to another, calling for such unilateral tinkering to stop.
Singerman also said TLS area, power, and timing QoR must be comparable to handwritten RTL results, adding that a 10% or 15% lower QoR with TLS would be acceptable. He concluded by noting that a good tool is only one piece of this puzzle.

It was no surprise that the four other panelists touted TLS as ready today. NEC assistant research manager Benjamin Carrion Schafer said the company has used TLS in a production flow since 1993 and discussed the abstraction gap that exists between the virtual prototype and RTL designs today.
Xilinx distinguished engineer Vinod Kathail described TLS tools as mature and integrated, and with a QoR comparable to handcrafted RTL. TLS adoption increases productivity as defined by faster time to results, the ability to perform design-space exploration, and easy migration across device families, Kathail said.

Mark Warren of Cadence admitted that it takes four months for someone to become proficient in C++ and four more days to add SystemC skills, but he added that a designer proficient with TLS tools could expect to achieve a 10% to 60% increase in QoR. He attributed the QoR improvement to the ability to perform micro-architectural exploration and a 35% to 50% reduction in time to verified RTL.
Calypto’s Andres Takach said the company has productivity testimonials that show a fourfold to twentyfold improvement in verification and QoR optimization. According to Takach, 14 of the top 20 semiconductor companies now use TLS in multiple divisions.

When Meas asked how many of the panelists thought TLS was ready, the result was 100% predictable. When he asked the audience, very few were ready to provide an answer.