A novel approach for simulation of digital circuits using levelization
Verification had always been an important part of SOC design flow. As SOCs are getting more and more complex, so is their verification.
Verification of a design involves simulating the all possible aspects and functions of design. Out of various available simulation techniques, levelized simulation technique is one of the common techniques used by simulation tools. Applying the concept of levelization on combinational designs is not that difficult, but when it comes to sequential designs, it is challenging.
There are also some sequential designs which can't be simulated correctly even after levelization. This paper discusses the concept of levelization, its challenges and a generic approach for simulation of digital circuits that can be used even for simulating designs that fail in normal levelized simulation.1. Introduction to Simulation:
Simulation of a digital circuit, also known as logic simulation is the imitation of the operation of the design over time that requires a model, which is the design itself. Logic simulation of a design is done by using simulation software to predict the behavior of digital circuits and hardware description languages. As it allows the user to interact directly with the design, so it is the most natural way for the designers to get feedback on their design. Simulation techniques for logic circuits are used to predict changes in the values of output signals of design as a function of changes in the input signals. It can be performed at varying degrees of physical abstraction, such as at the transistor level, gate level, register transfer level (RTL), or behavioral level. Various techniques for logic simulation are there, one of them is the levelized simulation which is discussed in the next section. 2. Levelized Simulation:
In levelized simulation, the components of design are levelized first, that is, the components of a circuit are arranged in such a way that one component precedes a second component. Then the components can be evaluated in order. Evaluating components in correct order results in a faster simulation, because unnecessarily repeated evaluations are avoided.
Combinational designs can be easily levelized simulated, as simulation ordering is not an issue in such designs, but in case of sequential designs (asynchronous and synchronous), no such ordering is possible, for example in the case of a feedback loop where one component produces a signal that is an input signal for another component and the other component produces a signal that is input signal to the first component.
There are designs where more complicated feedback loops are also encountered. In case of feedback loops, special evaluation techniques are used which will be discussed in the later sections.