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Stars of DesignCon: Signal integrity in tricked-out, high-speed interconnects

R Colin Johnson -January 04, 2013

High-speed interface designers know there is no substitute for experience, but newer "black box" behavioral models--from rational approximation to neural networks--offer the ability to craft simulations in minutes that would take weeks using traditional physical-modeling techniques.

[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.]

Exactly how signal integrity engineers can combine traditional and behavioral black box models to trick-out their high-speed interfaces will be the subject of the DesignCon session, Modeling High-Speed Interconnects for the Signal Integrity Engineer: Tips, Tricks and Trade-Offs.

"Behavioral modeling allows signal-integrity engineers to sidesteps the time-consuming and error-prone process of building physical models," said John Dunn, who will speak at the session. "But though a black box is quicker to construct, it has distinct limitations that must be understood to be used effectively."


Caption: High-speed interconnects (top) can be modeled with RLC circuits (bottom) whose values can be tuned in order to debug and optimize circuit performance.

Dunn is an electromagnetic technologist at AWR Corp. (El Segundo, Calif.). The company specializes in high-frequency ICs and systems, including high-frequency EDA. It's a wholly owned subsidiary of National Instruments.

Since behavioral models can accurately reproduce all the measured stimulus-response characteristics of a high-speed interconnect, they can lull the unwary or inexperienced engineer into a false sense of security. In fact, a behavioral model never breaks the components inside the black box down into the typical resistive-, inductive- and capacitive-elements (RLC), which is necessary to debug and optimize typical designs.

"Behavioral models give the signal-integrity engineer absolutely no clue as to which dimensions need to be changed to make a design better," said Dunn. "All you can do is blindly change physical parameters and measure the results, with no understanding of where to start or what to change."

The experienced signal-integrity engineer has the advantage here, since previous designs that were successfully optimized may yield clues as to which dimensions need to be changed to improve performance. However, for the inexperienced engineer--or one new to behavioral modeling--the worst-case scenario is when signal-integrity problems are not even recognized before prototyping, resulting in extra cost and wasted time added to a project.

The better solution, according to Dunn, is to follow-up a behavioral model with a physical model for debugging and optimization. Physical models usually simulate a high-speed interconnect with RLC circuit elements whose values can be adjusted to debug problems and to optimize performance.

"Once a physical model is created, the signal integrity engineer can systematically change its various parameters to start understanding the physics of their interconnect better," said Dunn.  RLC lumped models can be tuned to enhance specific performance parameters, for instance, mitigating latency by reducing capacitance.

Info Redux:

Session: Modeling High-Speed Interconnects for the Signal Integrity Engineer: Tips, Tricks and Trade-Offs (works in Chrome)

DesignCon Registration (direct to registration page link):  Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.

And Don't Miss:  DesignCon Free Education & Training
(Host: Agilent Technologies; Corporate Sponsore: Rambus; Diamond Sponsor: SiSoft; Diamond Sponsor: Teledyne LeCroy: Platinum Sponsor: Rohde & Schwarz)

Monday, January 28:
•    Challenges and Solutions in Characterizing a 10Gb Device  (Agilent)
•    PCI Express 3.0 Characterization,Compliance, and Debug for Signal Integrity Engineers (Teledyne LeCroy)
    
Tuesday, January 29:
•    Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde &  Schwarz)
•    Ensuring Validation & Analysis of Complex Serial Bus Link Models  (Tektronix)
•    USB 2.0 Compliance Testing (Rohde & Schwarz)
•    Phase Noise and Jitter Measurements (Rohde & Schwarz)
•    True Differential S-parameter Measurements / Rohde & Schwarz
•    Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz)
•    USB 2.0 Compliance Testing (Rohde & Schwarz)
•    Phase Noise and Jitter Measurements (Rohde & Schwarz)
•    True Differential S-parameter Measurements (Rohde & Schwarz)
•    Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix)
•    Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB  (CST of America Inc.)

Wednesday, January 30:
•    Making DDR4 Work For You (Agilent)
•    Debugging to Find the Root Cause of Compliance, Limit or Mask Test Violations (Teledyne LeCroy)

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