Design Con 2015

Stars of DesignCon: Silicon Interposer Spurs 3-D Chip Stacks

January 14, 2013

The path to 3D chip integration is fraught with peril for unwary design engineers. Bridge technologies can help. For example, silicon interposers reap the high-performance, low-power, and high-density benefits of 3D, but avoid the manufacturing pitfalls of chip-to-chip stacking.

[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.]

"We designed our own 3D silicon interposer to focus on package test structures and manufacturing processes," said Mandy (Ying) Ji, system design engineer on Rambus Inc.'s silicon interposer project. "Our goal was to compare the electrical performance of all the different types of transmission lines and manufacturing processes for 3-D interposers."

Yi will be among the speakers at the DesignCon  session "3D Silicon Interposer Design and Electrical Performance Study," during which Rambus will present results of the project.

The challenge with direct chip-to-chip 3D is that the pin-outs of each die are derived from the top metallic redistribution layer (RDL) that ordinarily routes signals from driver transistors for off-chip communications. Driver transistors, however, are unnecessary for 3D chip stacks, since the through-silicon-via (TSV) is 100-to-1000 times smaller than the lines required for typical packages, thereby downsizing connectivity, reducing latency and cutting power consumption.

Unfortunately, chip-to-chip connections with TSVs requires drilling, etching, wafer-thinning and back-grinding on active die, which is expensive. However, by mating RDLs to TSVs on a passive silicon interposer--instead of the active chips--yields can be vastly improved while still reaping the main advantages of 3D in a safer and more economical architecture.



Caption: Rambus is working with the Industrial Technology Research Institute and the Advanced Stacked-System Technology and Application Consortium (Ad-STAC) on system integration using TSVs (pictured) and silicon interposers.

"Our first interposer has two die on the top and another die on the bottom," said Ji. "The two chips on top of the interposer communicate with each other using RDL, while the third chip on the bottom of the silicon interposer is interconnected with TSVs."

Rambus designed its first 3D silicon interposer as a test bed with which it could characterize different transmission-lines architectures for RDL communications, including stripline, microstripline, and coplanar waveguides, as well as various process technologies for TSVs.

"The two die on the top enable us to test chip-to-chip communications for different types of RDL transmission lines, while the third chip on the bottom allows different TSVs to be characterized," said Ji. "There are all sorts of alternative manufacturing processes, and we want to see how each will affect system performance."

Transmission lines were first modeled with a 3D field solver, then its results were compared with signal-integrity measurements for loss, impedance control, crosstalk and eye diagrams.


Info Redux:

Session: 3D Silicon Interposer Design and Electrical Performance Study

DesignCon Registration (direct to registration page link):  Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.

And Don't Miss:  DesignCon Free Education & Training
(Host: Agilent Technologies; Corporate Sponsore: Rambus; Diamond Sponsor: SiSoft; Diamond Sponsor: Teledyne LeCroy: Platinum Sponsor: Rohde & Schwarz)

Monday, January 28:
•    Challenges and Solutions in Characterizing a 10Gb Device  (Agilent)
•    PCI Express 3.0 Characterization,Compliance, and Debug for Signal Integrity Engineers (Teledyne LeCroy)
    
Tuesday, January 29:
•    Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde &  Schwarz)
•    Ensuring Validation & Analysis of Complex Serial Bus Link Models  (Tektronix)
•    USB 2.0 Compliance Testing (Rohde & Schwarz)
•    Phase Noise and Jitter Measurements (Rohde & Schwarz)
•    True Differential S-parameter Measurements / Rohde & Schwarz
•    Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz)
•    USB 2.0 Compliance Testing (Rohde & Schwarz)
•    Phase Noise and Jitter Measurements (Rohde & Schwarz)
•    True Differential S-parameter Measurements (Rohde & Schwarz)
•    Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix)
•    Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB  (CST of America Inc.)

Wednesday, January 30:
•    Making DDR4 Work For You (Agilent)
•    Debugging to Find the Root Cause of Compliance, Limit or Mask Test Violations (Teledyne LeCroy)

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