Smart power hook-up methodology for memories on SoCs

Paramjeet Singh, Shahab Akhtar, and Manmohan Rana, Freescale Semiconductor -January 16, 2013

SoC design comes with its own set of complications and challenges. One of the biggest challenges that arise is hard IP block integration and verification. As technologies are scaling, it is becoming more difficult to design IP blocks and then integrating them. In deep sub-micron technology designs, IR drop can often significantly impact the functionality.

In this paper, a new IR drop methodology is introduced which when used, results in a very robust internal power grid structure. Along with the robust design techniques, this IR drop methodology results in excellent Silicon results in terms of Vmin as low as 0.52V for 8Kx72 cut in Single Port High Speed RAM.

A memory generally contains four basic blocks - control, decoder, bit-cell array and I/O. The majority of the big drivers which sink more current are placed in the I/O, decoder and control blocks. So for proper functionality of each block we need to make sure that each driver gets sufficient voltage for its proper operation.

Figure 1: Basic Block Diagram of Memory


Generally, memory owners give some guidelines in the form of strapping frequency of the grid for all power rails to SoC designers for power hookup. Strapping frequency defines the distance between two consecutive metals straps (in top metal generally) on a given power line. Sticking to strapping guidelines while making the power grid ensures that almost all the drivers receive sufficient voltage to operate and hence good performance.

In Figure 2, power rails in M4 are vertical which is supposed to be hook-up by horizontal M5. In the target memory there are several power domains like VSSA, VDDP, VSS and VDDA.

Figure 2: Block Diagram of SoC Power Hook-Up

Suppose for a particular technology, a strapping frequency of 50 um is defined. It means that every 50 um, power line should be repeated for proper functionality and yield. In this case those drivers which face only one power line (vdd, vss) are worst affected by IR drop and hence there are chances of abnormal behavior being exhibited by these devices.

In Figure 3, the divider3 and divider1 see just one vdd / vss power line and hence might not receive enough voltage for proper functioning. Here divider2 sees multiple power lines and hence will operate properly.

In single-block memories, the use of just the strapping technique might be sufficient for proper operation. However, for multi-bank architecture memories or memories with long height and wide width, achieving IR drop requirements with only strapping will not be sufficient. And hence, in such cases we need something else along with strapping to help us achieve IR drop targets.

Figure 3: Power Hook Up in Long Height Memories

For normal functioning of these devices (dividers) a concept of offset is introduced and IR drop analysis is performed throughout the memory compiler for all possible combinations (like redundancy, source bias, DVFS, BIST etc). The above concepts will be explained in detail below. Here offset is defined as the distance between the first power line in top metal from the top of the memory instance or the distance between the last power line in top metal from the bottom of the memory instance. Hence, using the concept of both offset and strapping while making power grid on memory, can lead to improved IR drop.

Figure 4. Power Hook Up with Offset of 20 Microns

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