Design for manufacturing and yield
As designs move to the 28-nm and smaller nodes, the likelihood of a design being manufactured without defects trends toward zero unless a rapidly growing set of rules is adhered to. Those rules are increasing in number and complexity. The absence of extreme ultraviolet light sources means that double patterning has become essential and new devices, such as 3-D transistors, are being adopted. But it does not stop with just manufacturability. Lithographic features affect functionality and performance in such a way that yield has also become a primary concern.
Here we examine the problems and the ways in which increasingly sophisticated software can be used to overcome the limitations of technology. Representatives from five different companies discuss, from their own perspectives, these issues as well as solutions.
Why has it
become such an important topic?
Shrikrishna Mehetre, Director of Engineering, Open-Silicon
Major contributors to yield loss are:
- Geometric variations during the manufacturing process may result in performance variations that can push the device out of the allowed 3-Sigma variation, causing parametric yield loss.
- Specific patterns on the die may not get manufactured as desired because of diffractions that happen during the lithography process, causing catastrophic failures on the dies.
- Random defects may induce shorts or opens on the wafer, resulting in yield loss.
- The wafer goes through chemical mechanical polishing (CMP) after every interconnect and dielectric layer is deposited. Metal-density variations result in the thickness variations during the CMP process, which can accumulate errors and alter interconnect parasitics, causing yield loss.
Engineers can take precautions during the design process that would help reduce these effects. Logic designers can add either redundant logic or memory cells. These can be used to repair faults, which will increase yield even though the die is partly defective. There are tools and techniques used in the diagnosis of failures seen on silicon to ascertain the cause of the failures. This information can be used to correct layouts to improve the yield.
Additional steps are required in the physical and logic design flow. Logic designers can add additional test or diagnosis logic and implement redundancy for sensitive circuits, such as memory bit cells. Physical design engineers can ensure planarity of metals, litho-friendly design, redundant vias, and wire spreading to reduce failures on the die. Parametric yield loss can be addressed by using additional on-chip variation guard banding.
As the steps are added to the ASIC design flow for DFM/DFY, cost increases. The additional cost comes from the additional time required to plan, execute, and correct for these issues. There are additional EDA tools necessary to perform logical and physical checks for the design. It is important to see the ROI of such investments for a product. If the cost advantage from the increased yield is not significant compared with the investment done to achieve better yield, it is not worth spending those additional efforts. E.g. If the yield for stable technology nodes such as 130nm can be improved only by a fractional percentage and the cost incurred is high, it is not worth the investment. However, if another product on a smaller node like 28nm can get more than 5% yield improvement by implementing such DFM techniques, it may be worth the investment.
Another approach that can be considered is to do partial fixes. Addressing effects that affect yield the most, such as memory redundancy, redundant vias, litho-friendly routing, and pattern corrections, may have a greater impact compared with other DFM solutions. Designers can choose to selectively fix the DFM issues that provide the highest gains.
The role of package
modeling in DFM of
Siva P Gurrum and Manu Prakuzhy, Design for Manufacturing, Semiconductor Packaging, Texas Instruments
Semiconductor packaging is evolving from an enabling role to a differentiator in today’s electronic devices. Identifying a manufacturable design within the bounds of performance, reliability, and cost requirements is becoming ever more challenging. Advances in package modeling are providing means to predict a multitude of parameters related to performance, reliability, and cost.
Predictions from package modeling can be broadly categorized into performance and reliability. The cost of a packaging solution is typically derived from the design specification and manufacturing process flow. Performance parameters include thermal, such as thermal resistance values, and electrical, such as parasitics. In reliability, predictions typically cover risks and trends for the identified fail modes in a package family or package lifetime based on some of the fail modes. Predictions of both performance and reliability require correlations between model values and physical evaluations (Figure 1).
Figure 1 Building blocks of modeling correlations enable package design for manufacturing.
Modeling correlations are typically empirical relations between output parameters resulting from a model and physical parameters. Examples include: (a) the relationship between a model evaluation of the fatigue damage in solder joint and the physical number of temperature cycles to electrical failure, and (b) the relationship between electrical model prediction for the current density profile in a trace and the electromigration lifetime from physical tests. In some cases, physical parameters are directly predicted by a model, such as the junction-to-air thermal resistance of the package, or bond wire electrical parasitics. In these instances, correlations serve as a validation of the chosen approach for derivative designs.
For good modeling correlation, it is essential to incorporate the best modeling tools and techniques, accurate properties from material characterization, and the wealth of data from physical evaluations. Analysis tools are maturing, with customized tools now available for thermal and electrical, whereas the majority of mechanical tools are more general purpose, with longer cycle times. Material characterization must include bulk properties as well as properties sensitive to the physical structure and assembly of a package, such as the interfacial thermal resistance of a die attach material or the adhesion strength between interfaces. Also important is package characterization to bound manufacturing tolerances on critical parameters. An example is the die attach bond line thickness in a leadframe package, which critically affects delamination risk. Physical evaluations needed to complete a correlation include thermal resistance measurements, electrical testing on evaluation boards, and reliability testing according to standard specifications.
Some examples of design for manufacturing in packaging are:
- Bond wire pattern to eliminate shorts during mold flow for high wire density molded packages
- Lead finger design to minimize warpage and stress concentration near the bond wire stitch
- Layout of silicon chips on a die pad in a multichip module to minimize delamination stresses
- Thick metal content to reduce wafer warpage, which affects handling in assembly
- Metal content balancing in a substrate to reduce warpage, which affects assembly to PCBs
The role of modeling will grow to influence design, materials, and processes used in packaging.