Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success
The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the planning process. The era of a waterfall flow from RTL to GDSII was over long ago. Even the efforts to bridge the gap between the front-end and back-end design process, through tools and flows, are not always sufficient.
Modern SoC development requires a holistic approach and thorough planning starting at the design architecture of the SoC. The ASIC implementation process has to keep pace with the design complexity, performance, and time-to-market, all while ensuring first-time silicon success. These challenges, which are compounded by the advancement in the package technology and the complex foundry requirements at 40nm and lower nodes, make it essential to evaluate the design requirements and the technology limitations early on in the SoC design cycle.
Every team involved in SoC development must work cohesively for optimal planning and strategy. Large, complex designs with high performance requirements benefit from comprehensive planning up-front. These benefits include both predictability and reliability of results.
The most important aspect of planning and strategy is dividing the execution into different phases. These phases include technology, design flow, and SoC evaluation, exploring and identifying physical design challenges early, and finally physical design implementation. The physical design implementation team should thoroughly identify and define the entry and exit criteria at every phase. The learning from one phase should become the foundation for the next phase of the execution.
The definition of various phases and the criteria for entry and exit should align with the RTL design and verification process and their milestones. Hence communication between various groups involved in SoC development is crucial. The key is to thoroughly analyze and explore the design before the final implementation is executed on the fully-verified design to achieve predictable results in quality and schedule.
Technology, Design Flow, and SoC Evaluation
When the RTL design and verification is in the architecture stage, the physical design team should be engaging itself in evaluating the technology. This includes a thorough exploration of the process technology to learn its capabilities and limitations. Evaluating the technology libraries, determining the implementation tools and flows, and capturing the SoC requirements are a few of the fundamental and vital steps, which can be streamlined while RTL is being developed.
Library selection and its evaluation are very important for estimating the overall design performance. The designer must know the priority of optimization, such as speed, area or power. This priority will assist in determine what technology best suits the design needs. It also will assist in IP selection.
Different library vendors have a variety of offerings that include a mixture of threshold voltages, multiple channel lengths, and numerous metal stacks. It's important to evaluate and compare all of the offerings that apply to the SoC with respect to the target characteristics. This technology evaluation data can be used by system and RTL designer to write physically aware RTL and start early planning of physical limitations to the design. This also provides a baseline for the physical design team to create estimates of SoC area and power or evaluate the requirements of the SoC. All of these decisions must, of course, align with the business goals.
One of the first library characteristics to evaluate is the delay per stage of the standard cells. This data should be collected for all of the different types of standard cells in each of the threshold voltages that are available. Comparing the advantages of speed of the lower threshold voltage cells versus the higher threshold can assist in determining the mixture Vt cells that should be used in the design in order to obtain the lower power possible.
This data will also assist RTL designers to determine where to insert registers in their design. For very high performance designs that push the technology limits. The number of stages of logic between registers will be maximized. Knowing the number of stages that can be placed between registers will reduce timing closure iterations that require a loop from physical implementation back to RTL.
Figure 1 shows an example of the data collected to determine the delay for one stage. This example results in an average delay of 29ps per stage. The slop of the drawn line gives the corresponding stage delay