An insight into layout versus schematic
- Design rule check (DRC): It verifies whether the designed layout can be manufactured by the fabrication lab with a good yield.
- Layout versus schematic (LVS): It is a method of verifying that the layout of the design is functionally equivalent to the schematic of the design.
It is important to note that DRC does not ensure the intended functionality of layout. DRC is only limited to checking whether the given layout conforms to design rules provided by the fabrication unit so as to ensure the faultless fabrication but without warranting whether the circuit will behave in a way that it was intended to. The idea of LVS originated from this very requirement. In this article, LVS flow is discussed followed by common issues and their debugging with the help of appropriate illustrations.
How LVS works
A verification EDA tool performs LVS by taking a set of instructional code input, commonly known as LVS rule deck, in the following two steps: extraction and comparison. The LVS rule deck guides the verification tool by providing the instructions and identifying files which are needed for LVS. Design inputs needed for running LVS are as follows:
- Graphical database system (GDS) layout database of the design
- Schematic netlist of the design
- Cell definition file including Intellectual property files and standard cells
- Pad reference file
A LVS rule deck is a set of code, which is written in Standard Verification Rule Format (SVRF) or TCL Verification Format (TVF), which guides the verification tool to extract the devices and connectivity of the integrated circuit. The LVS rule deck contains the layer definitions for the identification of layers used in the layout file and matches description of a layer to the location of the layer in the GDS file. This helps in the recognition of the electrically connected regions in the layout, namely the nets. Nets are recognized from the layout shapes through analysis between layout shapes in layers. LVS rule deck also contains device structure definitions.
Figure 1 LVS flow
The LVS flow is as follows:
The verification tool takes the GDS file as input and breaks it down into basic design devices like transistors, diodes, capacitors, resistors etc. These devices are identified in the GDS file by recognition of the layers and shapes that makes up the circuit or by the cell definition of the devices/circuits provided in the cell definition file of the intellectual property blocks or in the LVS rule deck itself. It also extracts the connectivity information between these devices from the GDS file. The next step in connectivity extraction is uniquification of nets. Each electrical net is given a unique node number for identification during the extraction process. Net names can also be named based upon the presence of layout text objects or text statements in the control file. This device information along with their connectivity is written into a layout netlist file, generally called layout extracted netlist. This process is known as extraction.
In the comparison phase, the verification tool compares the electrical circuits from the schematic netlist and the layout extracted netlist. The netlist comparison process also uses the LVS rule deck. After the successful comparison between layout and source netlist, a one-to-one correspondence between the elements (instances, nets, ports, instance pins) of source netlist and layout netlist is established. The intention of the layout designer is to implement the functionality provided in the schematic into a geometrical representation of layout. Therefore, in order for the verification process to complete without error, both layout and source netlist must match. If the two netlists differ, discrepancies are reported in the form of a LVS result database which can be used to debug LVS issues. Result database would contain the list of incorrect elements and the reason of mismatch like incorrect nets, incorrect ports, and incorrect instances.
Commonly faced LVS issues and their debug
The source spice netlist which is a representation of the schematic of a circuit should match with the spice netlist extracted from the layout. But, there may be several reasons due to which LVS may fail. It is always suggested to check the following points in order to roughly find out the reason of LVS failure.
LVS comparison includes the following points:
- Number of devices in the schematic and its layout.
- Type of devices in layout and schematic.
- Number of nets in schematic and its layout.
Short in a design occurs when in a particular layer of the GDS two polygons having different layout text on them overlap and have a non-zero intersection. Alternatively, when two different nets touch each other, it will result in a short. Presence of a short in a design may result in a chip failure. In large designs, it is always suggested to run the short finding utility of the place and route tool before running LVS to figure out the shorts in the early phase of the design cycle. Presence of short in a design after running LVS can be identified as shown in the following example. In case of a short, LVS tool always dumps a report file which contains the information of the short.