Design planning for large SoC implemention at 40nm - Part 3
[Part 1 explores the process technology to learn its capabilities and limitations, including evaluating the technology libraries, determining the implementation tools and flows, and capturing the SoC requirements.
Part 2 covers comprehensive planning for complex designs at lower geometry.]
Floorplanning and PnR
A thorough exercise during physical architecture is the foundation for an efficient floorplan. It helps in reducing the overall turnaround time of the physical design phase. The broader prospective of the floorplan should be performed during the physical architecture phase, and the actual floorplaning phase should address the finer details of the floorplan, which impacts the physical design’s QoR.
The seed for a floorplan primarily comes from physical architecture, die size-power estimation exercise and the technology. When creating a floorplan, it’s important to consider some basic characteristics of the process technology. The designer should have explored the technology enough in the context of metal stack and metal configuration. Also the designer should have gained ample experience about the availability of vertical and horizontal routing resources and their requirements for the design as per the physical architecture.
At any level, creating “non-preferred” routing (i.e. not using the preferred routing direction for that level) is not recommended. In the case of a channel-based floorplan, when placing blocks, four-way intersections in top-level channels should be avoided; “T” intersections create much less congestion. This consideration can be critical in leaving adequate space for routing channels, especially if there is not much opportunity for over-the-cell routing. Using fly lines can help determine optimal placement and orientation, but when the fly lines are numerous enough to “paint the area” between blocks, designers must rely on their best judgment for block placement, and later evaluate the results for possible modification.
Once blocks are placed, block-level pins may be placed. It is necessary to determine the correct layer for the pins and spread the pins out to reduce congestion. Placing pins in corners where routing access is limited should be avoided; instead, multiple pin layers for less congestion should be used. It is worth spending the time needed to place block pins manually so that block-to-block routs are straight, have minimum distance between them and are cross-talk immune. This will help immensely down the line during full-chip timing closure.
While placing the hard macros, like PLL or other analog blocks, it is important to adhere to the guidelines provided by the IP vendor. Placing cells within the perimeter of hard macros is not recommended. To keep from blocking access to signal pins, it is a good idea to avoid placing cells under power straps unless the straps are on high metal layers (i.e., higher than metal2). Density constraints or placement of blockage arrays may be used to reduce congestion since these strategies will help spread cells over a larger area, thereby reducing the routing requirements in that area.
In any physical design work, it is essential to understand the requirements of the target process technology. Lower utilization would result in a larger chip, but the chip is less likely to have problems in routing. For example, most processes now require the insertion of holes in large metal areas in a step known as “slotting” or “cheesing.” Slotting relieves stress-related problems in the metal due to thermal effects, but may change the metal’s current-carrying characteristics. It is imperative to consult the design rule document for this and many other physical variables.
For technology nodes below 40nm, there are other important rules that must be considered while creating the floorplan. For example, the TCD structures are placed to monitor the various processes on the die. These components are driven from the foundry. The TCD structure is required to be placed at regular intervals throughout the chip. It could be a significant size, which may need to be allocated on the die early on. This may impact a floorplan of a block at a later stage if this fact is not considered early on, such as in a block packed with memories. Similarly, for core ESD protection, it is recommended to place ESD clamps at regular intervals on the die. These are a few of the mandatory components that must be considered in the early stages of full-chip floorplanning, and must be considered for block-level floorplanning.
The RTL should be examined for logical models to break out into hierarchical physical elements. If there are multiple instances of any logical hierarchical element, these elements can be grouped to form one physical element. It is easier to floorplan with same-size blocks, so small blocks should be grouped and large blocks divided when appropriate. Working with “medium-sized” blocks is typically best; six to twelve roughly equivalent-sized blocks is a reasonable target.
Typically, floorplans should be started with I/Os at the periphery (depending on the package design). It is crucial to determine the total number of I/Os required, and their placements. The physical designer must calculate the number of core Vdd and Vss pads in the I/O ring for ESD protection (in the case of a flip chip). In the case of a wire-bond chip, the core Vdd and Vss must be calculated through a thorough analysis after considering the chip power requirements and IR drop. The SSO ratio must also be considered for calculation of VddIO and VssIO; care must be taken for high-speed interfaces. Apart from this, there could be some custom requirements for I/O planning, such as the placement of PLL in the I/O rings or placement of SerDes IP or DDR IP, which is inclusive of bumps in it. During and after the I/O planning, it is very important that the bump or bond pad DRC and LVS is clean before a floorplan can be considered final. Hence, I/O planning is yet another seed for floorplanning.
It is best to place parts of the design that have special layout requirements (e.g., memories, analog circuitry, PLLs, logic that works with a double-speed clock, blocks that require a different voltage, any exceptionally large blocks, etc.) first to ensure that their needs are accommodated. Design blocks with special needs must be understood at the beginning; for example, flash memory has a high-voltage programming input that must be within a certain distance of an I/O pin, so it is best to place this element first.
If there are two or more large blocks or other features that make a reasonable floorplan impossible, it may be necessary to increase the die size or re-arrange I/Os. Finding this problem early in the flow enables and easier business decision about whether the chip will be financially viable with a larger, more expensive die. If any of the large blocks are soft (synthesizable) IP or otherwise available as RTL, it might be possible to avoid going to a larger die by repartitioning that block into smaller pieces.
Another key aspect in I/O planning is to consider the scan I/O requirement. Here, the physical designer must engage with the DFT architect. The scan architecture could also play a significant role in I/O planning and floorplanning.