Increase the range of memorized voltage for a sample-and-hold device
Yakov Velikson, Lexington, MA; Edited By Martin Rowe and Fran Granville - January 22, 2009
Sample-and-hold devices find use in front of ADCs. The basic sample-and-hold circuit comprises two op amps, A1 and A2; a switch, S1; and a capacitor, C1 (Figure 1). For many low-power op amps, the values of the input and output voltages can be only ±10 to ±14V using a standard ±15V power supply. Enabling these devices to handle greater voltage can significantly improve the resolution of an ADC.
You can increase the memorized voltage that amplifiers A1 and A2 can reach by using a variable power supply (reference 1 and reference 2). This approach places additional voltage requirements on S1, however. To continue using switches with the same range as the original, you must add two switches and independent control-logic blocks, CL1 and CL2, for switches S1, S2, and S3 (Figure 2). The two parts of the circuit may have independent power supplies. You apply the same variable voltages to amplifiers A1 and A2 as you do to control-logic blocks CL1 and CL2, respectively. When S1 and S3 are closed, S2 is open, and vice versa.
The resulting circuit keeps the voltages connected to the gate and substrate for the MOS transistors of each switch within the desired 30V range (Figure 3). (You derive this value from the sum of absolute-voltage values: |V1|+|V2| and |V3|=|V4|.) Voltages V1 and –V2 connect to amplifier A1, control-logic block CL1, and the substrates of the transistors of switches S1 and S2. Voltages V3 and –V4 connect to amplifier A2, control-logic block CL2, and the substrates of the transistors of switch S3.
You create the changing voltages of V1 and V2 using resistor dividers R5 and R6 and R7 and R8, which connect to the 30 and the –30V power supplies and the output of amplifier follower A1 (Figure 3). Transistors Q1 and Q2 create the change to the power supply of amplifier A1. Voltages V1 and V2 also supply power to control-logic block CL1 and the substrates of the transistors of switches S1 and S2. CL1 comprises transistors Q11, Q12, Q15, and Q16. It creates a control signal for gates Q5 and Q6 of switch S1 and the inverse signal for gates Q8 and Q9 of S2.
Resistor dividers R9 and R10 and R11 and R12 connect to the 30 and the –30V power supplies, and the output of amplifier follower A2 creates the changing voltages V3 and V4. Transistors Q3 and Q4 create the change to the power supply of amplifier A2. Voltages V3 and V4 also supply power to control-logic block CL2 and the substrates of the transistors of switch S3. CL2 is made up of transistors Q13, Q14, Q17, and Q18. It creates a control signal for gates Q7 and Q10 of switch S3. Transistors Q5 through Q10 and Q11 through Q18 of CL1 and CL2, respectively, are complementary pairs of MOS logic transistors.