Hartley oscillator requires no coupled inductors
Examine a traditional Hartley oscillator circuit, and you'll note its trademark: a tapped inductor that determines the frequency of oscillation and provides oscillationsustaining feedback. Although you can easily calculate the total inductance required for a given frequency, finding the coupling coefficient, k, poses technical difficulties and may require experimental optimization, also referred to as the "cutandtry" method. This Design Idea presents an alternative equivalent circuit that allows you to model the circuit before building the prototype.
Figure 1 shows the Hartley oscillator's equivalent tuned circuit and component values for an 18MHz oscillator. The mutual inductance is For the equivalent circuit, the equations are: L_{A}=–L_{M}, L_{B}=L_{2}–L_{A}=L_{2}+L_{M}, and L_{C}=L_{1}–L_{A}=L_{1}+L_{M}. The rest of the equations for the equivalent circuit are:
and
Unfortunately, a truly equivalent circuit requires a negative inductance, L_{A}. However, for frequencies near the resonant frequency f_{0}, you can replace the negative inductor with a capacitor as (Figure 1c), where C_{A} replaces L_{A}. Note that the equivalent circuit's derivation neglects parasitic winding resistances and capacitances.
Figure 2 illustrates an oscillator and output buffer using the equivalent circuit. When constructed, the circuit generally performed as expected from an initial Spice simulation. During testing, several components' values required tweaking, and multiple iterations of Spice analysis ultimately yielded the final design.
The oscillator's tank circuit consists of L_{B}, L_{C}, C_{4}, and C_{5}, plus the capacitance provided by the voltage divider C_{6}, C_{7}, and C_{8}—approximately 6 pF, including Q_{1}'s and Q_{2}'s input capacitances and some stray capacitance. The total tank capacitance of 66 pF approximates the calculated value of 67 pF. Capacitors that connect to the tuned circuit feature ceramicdielectric construction with NP0 temperature coefficients.
Inductors L_{B} and L_{C} consist of aircore coils mounted with their axes at right angles to each other to minimize stray coupling. However, vibration affects their inductances, and, in a final design, both should consist of windings on dielectric cores or on toroidal cores, providing that the toroids' temperature coefficients of inductance are acceptable for the intended application.
The information in Reference 1 provided basic designs for both inductors, and adjusting the spacing of their turns tuned the oscillator to exactly 18 MHz. For a more rigorous design, you can measure the inductors before installation, but parasitic effects may require some adjustment of the inductors.
The capacitive voltage divider, C_{6}, C_{7}, and C_{8}, applies the proper signal levels to Q_{1} and Q_{2}. Because the divider's effective capacitance as "seen" by the tank circuit amounts to only 6 pF, you can replace the remaining 60 pF consisting of C_{4} and C_{5} with a variable capacitor if the design calls for a tunable oscillator. In this example, the output stage consisting of Q_{3} and its associated components would require modification to provide more bandwidth if the oscillator requires a tuning range exceeding ±2 MHz.
Capacitor C_{3} bootstraps Q_{1}'s Gate 2 to its source, which provides additional gain and reduces Q_{1}'s Gate 1 input capacitance below its alreadylow value of approximately 2.1 pF (Reference 2). An 8.3µH inductor, L_{2}, of less than 2Ω dc resistance connects to Q_{1}'s source and presents a relatively high impedance at 18 MHz and provides a dc path from Q_{1}'s source to ground through R_{3}. At 18 MHz, L_{2} has an impedance that consists of an inductive reactance of about 940Ω in parallel with a resistance of about 3.5 kΩ, which results in a verylowQ choke. Provided that its inductance and reactance approximate L_{2}'s original values, you can substitute a physically smaller inductor for L_{2}. Inductor L_{1}'s properties are less critical, but it should present a low Q of 4 to 6 and a dc resistance of approximately 5Ω or less. You can use a standardvalue choke for L_{1} if it meets these requirements.
Source follower Q_{2} drives the output stage, which uses a pimatching network to transform the 50Ω output load to 285Ω at the collector of Q_{3}. Bootstrapping Q_{2}'s Gate 2 by onehalf of the stage's output voltage increases the source follower's gain and dynamic range and reduces its input capacitance.
You can use potentiometer R_{15} to adjust the circuit's output level from about 0.9V pp to approximately 1.5V pp across a 50Ω load. At a constant room temperature of about 23°C, the frequency remains stable, and the circuitry that controls output level remains stable even with no load on the output. For a fixedfrequency application, the output circuit's loaded Q of 4 provides adequate bandwidth to eliminate retuning of the output circuit for small changes in frequency.
To set the output level to a safe maximum, connect a 50Ω load to the output, and then adjust the output to 1.5V pp. The draintosource voltage applied to Q_{1} will remain at a safe level for all loads from 50Ω to no load, even though the outputvoltage level increases as the load resistance increases. To avoid exceeding Q_{1}'s specified maximum 12V draintosourcevoltage rating, do not exceed an outputvoltage setting of 1.5V into a 50Ω load. Note that zener diode D_{1} reduces Q_{1}'s drain voltage to provide an additional safety margin.
In a previous Design Idea, an operational amplifier and a dioderectifier circuit set the oscillator's gain through a control voltage applied to Q_{1}'s Gate 2 (Reference 3). In this design, a simple passive circuit serves the same purpose. A portion of the signal at Q_{3}'s collector drives a voltage doubler consisting of D_{2}, D_{3}, C_{20}, and C_{21}. Part of the negative voltage developed by the voltage doubler drives the junction of R_{18} and C_{19}, the controlvoltage node, which also receives a positive voltage from variable resistor R_{15} through R_{17}, and the resultant voltage sets the output signal level. At startup, only a positive voltage is present at Q_{1}'s Gate 2, and Q_{1}'s maximum gain easily starts the oscillator. When the output reaches a steady state, the control voltage reduces and maintains oscillation at the signal level determined by the output level control.
REFERENCES 

System level design and integration challenges with multiple ADCs on single chip
Understanding the basics of setup and hold time
Product Howto: Digital isolators offer easytouse isolated USB option
Managing noise in the signal chain, Part 2: Noise and distortion in data converters
War of currents: Tesla vs Edison
Simple reversepolarityprotection circuit has no voltage drop
Control an LM317T with a PWM signal
Start with the right op amp when driving SAR ADCs