Reducing PDN impedance at high frequencies

-March 31, 2015

This paper discusses the importance of low PDN (power-distribution network) impedance on high-speed PCBs, and the ways to achieve lower impedance at high frequencies. The study is conducted with post-layout power integrity analysis using Mentor Graphics Hyperlynx.

 

Introduction

It is important to keep the PDN impedance on a PCB low to minimize the generation of switching noise due to transient current in ICs connected to the power rail. With reference to equation (1), transient current in an IC interacts with PDN impedance and generates switching noise. This noise is induced to the power rail and could cause jitter, SI (signal integrity), and EMI (electromagnetic interference) problems.

      Noise ripple = transient current × PDN impedance                 (1)

With reference to Figure 1, the impedance of each PDN element is lumped together and forms the impedance of a particular power rail. The VRM (voltage regulator module), bulk bypass capacitors, and decoupling capacitors contribute to impedance at frequency range from low (kilohertz) to medium-high (<400MHz). Impedance at higher frequencies (>400MHz) is mainly contributed by plane capacitance and loop inductance (orange curve in Figure 1).

Figure 1. Impedance profile of PDN elements

 

This paper focuses on the effect of loop inductance and plane capacitance, and how they are manipulated to achieve lower PDN impedance in the high frequency domain. The effect can be achieved by proper placement of decoupling capacitors and applying thinner substrates between layers of power and ground planes. The study is conducted with post-layout PI (power integrity) analysis using Mentor Graphics Hyperlynx.

Proper placement of decoupling capacitors

With reference to the cross-sectional view of a PCB with IC and decoupling capacitor (<<1uF) illustrated in Figure 2, Loop 2 (the loop inductance) becomes larger when the capacitor is placed further away from the IC; this in turn increases the PDN impedance at high frequencies.

Figure 2. Loop inductance

 

With reference to Figure 3, some decoupling capacitors (green) are placed under the BGA IC, and some are placed far away from the IC. On the other hand, in Figure 4, all decoupling capacitors are placed under the BGA IC.

Observing the impedance profile in Figure 5 for power nets with capacitor placement shown in Figure 3 (i.e., higher loop inductance) and 4 (i.e., lower loop inductance) respectively, it is obvious that when all the capacitors are placed directly under the BGA using via-in-pad (i.e., minimum trace connection), the parasitic interconnect inductance is tremendously reduced, resulting in the blue impedance curve with lower magnitude.

The hardware designer should consider using smaller capacitor package size (0402 or smaller) or HDI (high density interconnect) PCB technology in order to fit all decoupling capacitors directly under the BGA IC to achieve minimum loop inductance and PDN impedance.

Figure 3. Decoupling capacitors (PCB bottom layer) partially placed under BGA IC (PCB top layer)

 

Figure 4. All decoupling capacitors (PCB bottom layer) placed under BGA IC (PCB top layer)

 

Figure 5. PDN impedance based on effect of loop inductance

 

Thinner substrate between power and ground planes

By applying a thinner dielectric between power and ground planes, not only is loop inductance reduced, but also plane capacitance is increased, as governed in equation (2), which in turn results a lower PDN impedance.

C = ε A / d                    (2)

C = plane capacitance

ε = substrate property

A = overlapped conductive area between power and ground planes

d = substrate thickness between power and ground planes

 

The effect of substrate thickness is studied by conducting post-layout PI analysis on PCB with stackup shown in Figure 6, where power net of interest is laid out on layer 6, with reference to ground plane on layer 8. Substrate thickness between layer 6 and 8 is plotted for 10 mils & 30 mils (Figure 7).

Figure 6. Stackup of example PCB

 

Figure 7. PDN impedance variation with substrate thickness


Conclusions

Proper decoupling capacitor placement and stackup planning are crucial to obtaining a low PDN impedance at high frequencies.

 

References

[1] "Power Distribution Network Planning", by Barry Olney, In-Circuit Design Pty Ltd Australia

[2] "Basic Concepts of Power Distribution Network Design for High Speed Transmission", by F.Carrio, V.Gonzalez and E.Sanchis

[3] High-Density Interconnect

 

Also see:

 

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