PAM-4 PCB best practices
400 gigabit Ethernet (400GbE) is a new generation wired communication standard supporting the projected explosion in data traffic volume with the booming applications of Internet of Things (IoT) and 5G mobile broadband [1]. In the implementation of 400GbE communication, electrical interface with 4-level pulse amplitude modulation (PAM-4) signaling over 8 lanes is adopted. The combination of 8 lanes at 50Gbps per lane enables the total bandwidth of 400Gbps over the Ethernet [2]. The electrical specifications of 400GbE with 50Gbps (i.e., 25GBaud) PAM-4 signaling are defined by IEEE 802.3bs [2] [3].
PAM-4 has 4 digital amplitude levels, as shown in Figure 1. Its advantage over NRZ is that each level or symbol in PAM-4 contains two information bits, providing twice as much throughput for the same baud rate [4] [5].
Figure 1 NRZ versus PAM-4, which provides twice as much data throughput for the same baud rate.
Key design practices from the power integrity perspective
Once switching noise on the PDN is coupled into the transceiver IC’s power plane, jitter will be induced in the transmitted signal, which could increase the bit error at the receiving IC. To keep the noise ripple small and within design specification, PDN impedance shall be kept below the targeted impedance, which is governed by Eq. (1) [6].
(1)
Vripple_{max} = maximum ripple at power rail
I_{max} = maximum current loaded by ICs
To minimize PDN impedance, elements on PCB such as decoupling capacitors, interconnection inductance and power plane capacitance require special attention. Decoupling capacitors shall be mounted near the high speed transceiver power pins to reduce the PDN impedance which in turn attenuates the noise from external sources (e.g., voltage regulator and other switching ICs) before the noise can be coupled into the transceiver IC package power plane. The noise at the high speed transceiver power pins shall be less than 10mVpp. The recommended minimum capacitor quantity for high speed transceiver power pins on Xilinx FPGA is shown in Figure 2, where one 4.7uF ceramic capacitor is mounted near each high speed transceiver power supply group (i.e., MGTAVCC, MGTAVTT and MGTVCCAUX) [7].
Figure 2 Recommended capacitor quantity for high speed transceiver power pins on Xilinx FPGA
PDN impedance gets lower when interconnection inductance is decreased. The interconnection inductance is mainly contributed by the parasitic inductance of the traces connecting the capacitor's mounting pads and the vias. With reference to cross sectional view of a PCB illustrated in Figure 3 [6], the interconnection inductance is formed in each interconnection loop labeled as Loop 1, 2 and 3 respectively. The decoupling capacitors shall be mounted as close as possible to the IC power pins to minimize the interconnection inductance.
Figure 3 Interconnection inductance within PCB
On the other hand, PDN impedance becomes lower when the plane capacitance formed between the power and ground in PCB stackup is increased. Referring to the basic model of plane capacitance illustrated in Figure 4 and Eq. (2), capacitance is increased by decreasing the thickness between the parallel planes, enlarging the area of parallel planes between power and ground, or using substrate with higher dielectric constant.
Figure 4 Basic model of plane capacitance in PCB stackup
(2)
ε_{r} = dielectric constant of substrate
ε_{o} = permittivity of vacuum
w = copper width
l = copper length
d = substrate thickness
Key design practices from signal integrity perspective
According to guidelines, a PAM-4 channel with trace length up to 8 inches on a printed circuit board (PCB) shall have insertion loss less than 10dB at 14GHz and 20dB at 28GHz respectively [3] [8] in order to achieve seamless data communication between the transceivers. There are seven key design practices from a signal integrity perspective discussed in the following sub-sections.
A. Selecting low loss material for PCB substrate
There are 3 types of PCB substrate dielectric materials categorized based on the dielectric property (e.g., loss tangent and dielectric loss). With reference to Table 1, high loss material (e.g., Nelco N4000-6) has loss tangent above 0.02 and dielectric constant above 4, medium loss material (e.g., Isola FR408) has loss tangent about 0.01 and dielectric constant between 3 and 4. Meanwhile, low loss material (e.g., Duroid 5870) has loss tangent about 0.001 and dielectric constant below 3. Dielectric attenuation is directly proportional to the loss tangent and square root of dielectric constant, as shown in Eq. (3) [9].
Table 1 Category of dielectric materials
Materials | Dielectric constant | Loss tangent | Example |
High loss | 4.3 | 0.023 | Nelco N4000-6 |
Medium loss | 3.6 | 0.01 | Isola FR408 |
Low loss | 2.33 | 0.0012 | Duroid 5870 |
Dielectric attenuation = 0.91 * f * loss tangent * √ε_{r} dB/cm (3)
ɛ_{r}_{ }= dielectric constant (Dk)
f = frequency in GHz
Based on calculation using Eq. (1) at 14GHz frequency and 8 inch trace length, the dielectric attenuation for high, medium and low loss materials is 12.35dB, 4.91dB and 0.47dB respectively. Referring to the guideline mentioned earlier (i.e., insertion loss less than 10dB at 14GHz for trace length up to 8 inches), low loss material shall be selected to allow more headroom contributed by other channel losses.
B. Minimizing via stub
When a via is used to connect the PCB trace to the IC, a blind, or back-drilled via (i.e., in Figure 5) shall be applied to minimize the stub length, which in turn pushes the quarter wave resonant frequency higher, thereby increasing the bandwidth of the PHY link. With reference to Eq. (4) [10], the quarter wave resonant frequency is inversely proportional to the stub length. Rearranging Eq. (4) and (5) [11], for 50Gbps (i.e., 25GBaud/s) PAM-4 transmission on PCB with low loss material, where Dkeff is 2.33, the maximum stub length would be ~16 mils.
Figure 5 Blind or back-drilled via
Where:
f_{o} = quarter wave resonant frequency (Hz)
c = speed of light (~12 inches/ns)
stub_length in inches
D_{keff} = effective dielectric constant
C. Minimizing impedance mismatch due to surface mount pad of AC coupling capacitor
The surface mount pad of the AC coupling capacitor has wider copper compared to the PCB trace. For instance, capacitor in 0402 package has 20 mil pad width, while 0603 package has 30 mil pad width [12]. With reference to the 3D model of surface mount pad of capacitors in series with 100 ohm differential traces illustrated in Figure 6, a signal that propagates along these traces with 6 mils copper width, encounters an impedance discontinuity once it arrives at the surface mount pad with a wider copper (e.g., 30 mils width for 0603 package). Referring to Eq. (6) and (7) respectively [13], a larger copper’s cross sectional area increases the capacitance, which in turn causes capacitive discontinuity (i.e., dip) to the characteristic impedance of the transmission line.
With reference to time domain reflectometry (TDR) and Sdd21 plots shown in Figure 7, a wider pad contributes to a larger impedance discontinuity, which in turn causes a larger insertion loss due to more severe signal reflection. The attenuation at 14GHz due to 0603 (i.e., 1.2dB) and 0402 (i.e., 0.4dB) packages are at least double of 0201 (i.e., 0.2dB). Hence, designers ought to use capacitors in a smaller package, e.g., 0201 (i.e., 10 mil pad width) to minimize the discontinuity.
(6)
Where:
L_{o}= intrinsic loop inductance per unit length of the transmission line (in nH/cm)
C_{o}= intrinsic capacitance per unit length of the transmission line (in pF/cm)
Z_{o} = characteristic impedance (in ohm)
(7)
Where:
C = capacitance (in pF)
ε_{r} = relative permittivity of substrate
ε_{o} = permittivity of vacuum
w = width of SMT pad (in cm)
l = length of SMT pad (in cm)
d = distance between SMT pad and reference plane underneath (in cm)
Figure 6 Surface mount pads of capacitors in series with differential traces modeled in Keysight EMPro.
Figure 7 TDR and Sdd21 of varying surface mount pad width in series with 500 mil long PCB trace simulated in Keysight EMPro.
D. Providing continuous reference plane
When the PCB trace crosses over a gap between 2 split planes (i.e., gap shown in heavy black line in Figure 8), an inductive impedance discontinuity or imperfect reference is encountered. This phenomenon is governed by Eq. (6) and (8) [13] respectively. To study the effect of imperfect reference, 3D model of the transmission line that crosses over the split planes shown in Figure 9 was constructed and simulated in EMPro. The microstrip differential traces cross over the gap with 100 mil length and 250 mil width. The gap depth is the measured distance between the microstrip differential traces and the solid plane on layer 3. When the gap is crossed over, the distance between trace and reference underneath is increased (i.e., current return path gets longer), this leads to the rise of inductance, which in turn causes the trace impedance to increase over the split. The negative impact of a non-solid reference plane on signal integrity is proven in the TDR and Sdd21 plots in Figure 10, where crossing over split planes results in higher insertion loss due to larger inductive impedance discontinuity. Hence, it is essential to ensure a solid reference plane along the entire trace length path.
Figure 8 Top view of PCB: signals crossing over split planes.
(8)
Where:
L = parasitic inductance of copper trace (in nH)
d = distance between copper trace and reference underneath (cm)
w = width of copper trace (cm)
t = thickness of copper trace (cm)
x = length of copper trace (cm)
Figure 9 Model of differential traces crossing over split planes in Keysight EMPro.
Figure 10 TDR and Sdd21 of 500 mil long PCB trace with solid reference versus crossing over split planes simulated in Keysight EMPro.
E. Minimizing signal crosstalk
Crosstalk causes noise induction in victim signals which in turn increases the bit error at receiving IC. Therefore, non-interleaved routing is applied on stripline, due to a lower FEXT compared to NEXT. Whereas interleaved routing is applied on microstrip due to a lower NEXT compared to FEXT [14]. Besides that, inter-pair spacing shall be at least three times the trace width [15].
F. Intra-pair skew
Intra-pair skew in PCB traces introduces higher insertion loss, which in turn increases the bit error of the PHY link. This is due to the fact that when inverting and non-inverting signals are not 180 degree out of phase, the eye height in differential mode becomes smaller. The impact of intra-pair skew on signal integrity is shown in Sdd21 plot in Figure 11, where larger skew leads to higher insertion loss. Therefore, each PHY link’s intra-pair skew shall be within 5mil to mitigate the transmission loss. The skew can be minimized using serpentine routing technique [16].
Figure 11 Sdd21 of 8 inch long PCB trace with varying intra-pair skew simulated using Keysight ADS.
G. Fiber weave
PCB dielectric substrate is composed of woven fiber-glass bound together with epoxy resin. The microscopic top view of PCB substrates of fiber weave styles 106 and 7628 are illustrated in Figure 12 [17]. The thick lines in light brown color are fiber glass weave patterns, while the square columns in black color are epoxy resin. A higher number of fiber glass style, e.g., 7628, refers to denser fiber glass weaving.
Figure 12 Fiber weave with fiber glass style 106 versus 7628, that make up a PCB dielectric substrate.
Fiber glass material has dielectric properties that differ very much from the properties of epoxy resin. For instance, NE-glass fiber has dielectric constant (Dk) and loss tangent (Df) 4.4 and 0.0006 respectively, E-glass fiber has Dk and Df 6.6 and 0.0012 respectively [17]. Meanwhile epoxy resin has Dk 3.2 [17], which is very much lower compared to fiber glass. When substrate of sparse fiber weaving is used, PCB traces could cross different regions of resin and fiber glass more frequently. As a result, the speed or propagation delay of the signal changes frequently along the trace from transmitting to receiving end. The relationship between them is governed by Eq. (9) [18].
(9)
Where:
v = signal’s speed on PCB (inch/ns)
c = speed of light (~12 inches/ns)
D_{k} = dielectric constant
This scenario poses a critical challenge to 50Gbps signal transmission. In the worst case condition for example, the trace of a non-inverting signal could be routed on fiber glass without crossing the resin region, while the trace of an inverting signal could cross many resin regions. As a result, due to the consistently changing propagation delay experienced by the inverting signal, the phase difference between non-inverting and inverting signals in common mode could be much less than 180^{o} at the receiving end. The large extent of skew or misalignment between the rising and falling edges leads to the reduction of width and height of the eye diagram. Ultimately, high bit error is experienced by the Rx. Hence denser fiber weave needs to be applied.
Almost Done
Please confirm the information below before signing in.
{* #socialRegistrationForm *} {* firstName *} {* lastName *} {* displayName *} {* emailAddress *} {* addressCountry *} {* companyName *} {* ednembJobfunction *} {* jobFunctionOther *} {* ednembIndustry *} {* industryOther *}