Using auto-zero comparator techniques to improve PWM performance (Part 1 of 2)
The use of an auto-zeroing comparator will eliminate the offset variation and, therefore, improve the accuracy of the zero-current detection. For the main PWM comparator, the use of an auto-zeroing comparator eliminates the control-loop offset between the error amplifier and the ramp-crossing level, thereby improving the overall system performance, especially at duty cycles that are less than 5%.
Lower power and high efficiency are the key priorities in power management today. Portable electronics need to conserve battery power and be able to operate over a wide range of input voltages. For PWM voltage regulators designed into portable systems, these requirements present design challenges as well as opportunities.
Two such opportunities exist for the use of auto-zeroing comparators in the design of power management systems. Using conventional CMOS comparators, such as the one shown in Figure 1, leads to complications both in the design as well as the layout, in order to keep offsets to a minimum. Auto-zeroing comparators can be used to keep system offsets to a minimum and improve the performance of the regulator system.
Figure 1: Conventional PMOS input-comparator design
(Click on image to enlarge)
RDSON Sensing Comparator
An important function of a voltage-regulator system is the ability to maximize power efficiency at various levels of load currents. One way of achieving this is for the regulator to know when it is running in the low-power, variable-frequency pulse mode during discontinuous conduction operation (inductor current goes to zero) and when to change into the fixed-frequency PWM mode for operation in the continuous conduction region (inductor current is always greater than zero).
During the variable-frequency operation mode, the regulator will output pulses in response to the ripple current through the inductor. This mode of operation is used during low current loading because the low-side FET can be turned off when the reverse current through the inductor is allowed to go to zero. At low current levels this mode of operation is more efficient than the PWM mode. A hysteretic comparator is used to compare the output voltage to a reference plus some degree of hysteresis. As the current load increases, the frequency of the control pulses increases as the output crosses the hysteresis threshold more frequently.
One of the problems with this architecture is that the system must be able to determine when the inductor current enters into the discontinuous-conduction mode of operation. This can be accomplished by placing a comparator that looks across the switch node, SW, and compares the voltage across the drain-source node of the low side FET with ground.
Figure 2 shows a block diagram of a typical application for a SW node RDSON sensing comparator.
Figure 2: SW node comparator application
(Click on image to enlarge)
In the figure, Transistor M1 is the high-side MOSFET and transistor M2 is the low-side MOSFET. As the inductor current passes through zero and becomes negative during the time that the low-side FET M2 is turned on, the voltage on the drain of the FET becomes positive.
The comparator senses this change, and reports back to the system that a discontinuous event has occurred. Most systems will count the number of times that this comparator reports this condition and after perhaps eight counts, the system will change modes. However, this type of a comparison for a conventional CMOS comparator (Figure 1) is a difficult challenge. The comparator must be able to respond to a few millivolts of input signal from the drain of the low-side FET in the presence of large amounts of ground noise.
If we take the example of a PWM regulator with a nominal output current of 5 A, we would like to set the discontinuous mode transition to begin at 0.1 × IOUT, or 0.5 A. If we choose a low-side power MOSFET with an RDSON of 40 mΩ, then the comparator will be looking at a signal of 0.5 A/2 × 0.04 = 10 mV. For CMOS integrated-circuit comparators, offsets can easily be in the 8 to 12-mV range or higher, depending on the layout. This variation will cause a wide distribution in where the controller senses the crossover point between continuous conduction and discontinuous conduction regions of operation, thus leading to possible yield loss.
Designing a conventional CMOS comparator to handle this job requires offset trimming and very careful layout. This type of comparator application is well-suited to an auto-zeroing comparator. Figure 3 shows a simplified schematic of an auto-zeroing comparator.
Figure 3: Simplified auto-zeroing comparator
(Click on image to enlarge)
The auto-zero comparator circuit is controlled by the DRIVE signal. During the auto-zeroing phase of operation, DRIVE is high and MN1 is connected across C1 by closing switch S1 and connecting switch S2 to ground. During this time, the voltage of MN1 is stored across the storage capacitor C1.
During the sampling phase of operation, the DRIVE signal is low and switch S1 is open and switch S2 now becomes connected to the input node, SW. When SW is below zero volts, MN1 is pinched off by the voltage on C1, allowing I1 to pull up on the drain of MN1. Once SW crosses zero volts, MN1 turns on and begins to pull down the gate of MN2, thus causing the COMPOUT node to change state.
The obvious advantage of this circuit is to null the part-to-part variations in the offset of transistor MN1. The advantage of this circuit is that the input to the comparator is connected to ground during the noisy transition between the high-side power FET turning off and the low-side power FET turning on. The DRIVE signal is only changed to the sample mode when the low side FET is in the full-on condition.
A further advantage of this architecture is that the comparator input is disconnected from the SW node during the time that the high-side FET is on. In a portable computer application, the SW node voltage could go as high as the charger output voltage of around 20 V. Using a conventional comparator, you would need to place an additional high-voltage switch in series with the comparator input in order to protect it.
(Part 2 of this article looks at the PWM comparator in more detail, and the resultant performance. read it by clicking here.)
About the author
Stephen W. Bryson is a Principal Design Engineer at Fairchild Semiconductor Corp. San Jose, CA. He has published several papers and has patents in the area of power management and drivers. He has a BSEE degree from Oregon State University and a MSEE from Santa Clara University.