Editor’s note: We bring you chapter 5-Buck Converters of "GaN Transistors for Efficient Power Conversion", published by Power Conversion Publications. The authors delve into various buck converter designs using GaN FETs as the foundational part of the design architecture. Previously, we saw Chapter one, “Gallium Nitride (GaN) technology overview” and Chapter six "Isolated full bridge converters"
For applications requiring high power density and high power, but not requiring electrical
isolation, the buck converter has been the workhorse topology for many years. Computers, servers, telecom equipment, satellites, medical equipment, and industrial equipment all use these simple, low cost, high performance DC-DC converters to power a wide variety of loads – mostly high performance digital ICs such as microprocessors, memory, DSPs, and ASICs of all types.
Improvements in buck converters over the past few years have been limited by the power MOSFET’s sedate switching speeds which, in this “hard-switched” topology, translates into lower power conversion frequencies (size and cost), lower efficiency (size and cost), and lower VIN/VOUT ratios (less efficient power management systems). In chapter 5 we show that eGaN FETs unlock a new spectrum of performance that can be translated into significant power conversion system cost and performance improvements [1,2].
eGaN® FET Performance in Hard Switching Circuits
To drive frequency higher in a buck converter, especially at a high input voltage, power devices must have very low dynamic losses. The dominant component to the dynamic losses is the classic hard switching event where current commutates to the device turning on before the voltage across that device collapses. This event is shown in figure 5.1, and is reversed during turn off of the high side device. The energy of each switching period is approximated by:
ESW = VIN x IOUT x t, where t is determined by the various components of the device gate charge (QG), device series gate resistance (RG), driver impedance, drive voltage, inductance common to the power and the drive loops, and device transfer characteristics. Due to eGaN FETs requiring much less die area and having a lateral structure (see chapter 1), they have ultra-low gate and Miller charges (QGD). This, combined with a gate electrode designed to have low RG, make switching times for these devices very short, and energy dissipated due to classical hard switching very low.
There are four additional components that contribute to dynamic losses. These include diode recovery charge (QRR) where the energy loss (ERR) is equal to the recovery charge times the input voltage. A second is the output charge (QOSS) which has an energy loss (EOSS) determined by multiplying one-half of the output charge times the input voltage. Third, the energy loss (EG) associated with the gate charge (QG) is calculated as the gate charge times VGS. The fourth contributor to loss in energy is the reverse conduction voltage (VSD) and it is determined by the following equation: ESD = VSD x IOUT x tR (where tR is the total reverse conduction time).
Figure 5.1: Classical hard switching waveform.
To determine the total energy loss, or power dissipation, the sum of these individual four components combined with the energy loss in each switching period is multiplied by the frequency.
PDYN = f x (ESW + ERR + EOSS +EG + ESD)
eGaN FETs, unlike standard power MOSFETs, have no minority carriers to be stored in a junction, and therefore no QRR. The output capacitance, COSS, and charge, QOSS, is also smaller because eGaN FETs are physically smaller than MOSFETs of comparable RDS(ON).
Both VGS and QG are low, so EG is negligible for eGaN FETs. Finally, due to the reverse current conduction mechanism, eGaN FETs have a high VSD when compared with the body diode forward voltage of a MOSFET. This condition has the potential to increase the energy loss ESD and is influenced by the total reverse conduction time, a condition that can be controlled by the time that the rectifier-switch is acting like a diode .
The basic buck converter circuit is shown in figure 5.2. The higher the ratio of input voltage (VIN) to output voltage (VOUT), the greater the benefits of using eGaN FETs become, since most of the components contributing dynamic losses are related to VIN. This voltage is converted down to the required voltage, often powering a microprocessor, memory or other power-bus voltage using a single stage buck converter.
Figure 5.2: Basic buck converter circuit.
Four different eGaN FET based buck converter designs were compared against state-of-the art MOSFET counterparts to demonstrate the improvements that can be expected over a wide range of operation.
1) 48 VIN – 1.2 VOUT
2) 19 VIN – 1.2 VOUT
3) 12 VIN – 1.2 VOUT with 2 parallel eGaN FETs
4) 60 VIN – 10 VOUT
Measurements were taken at frequencies from 300 kHz up to 1 MHz.