Easier tuning for load transient in power supplies for high power CPUs
Salvatore Galati - February 13, 2013
How we solved the time consuming problem of tuning for load transient, in power supply applications for high power CPUs
In dc-dc voltage converters, one of the most challenging rails is the CPU. The CPU has current transients with very high current steps, and high slew rates. The CPU rail also requires output capacitors that can sum up to several mF (typically around 4mF), which increases the size and cost of the solution.
Controller vendors have come up with improvements to reduce the number of output capacitors and so save money in the solution’s overall BOM. These improvements often consist of having non-linear loops in parallel to the main control loop.
The non-linear loops turn on all the phases at the same time, asynchronously, when they detect a transient. Depending on the vendor, some sense the remote Vout to trigger this event, some the output of the Error Amplifier. The necessity of a non-linear loop is also based on the fact that, for EMI concerns, the design community prefers Voltage Mode to Constant-On Time control.
Below in Figure 1 are two graphs that illustrate how the non-linear loop works. On the right is a system where a current transient takes place; Vout drops and the phases of the controller stay synchronous. On the right, with the non-linear loop, when the transient happens, all the phases are on for one pulse asynchronously. Load Transient Boost (LTB) is STMicroelectronics’ name for their non-linear loop.
This idea of a Voltage Mode control with a non-linear parallel loop works well and serves to save a few output capacitors.
For example, in Figure 2 below, we show two measurements of a board, without changing any of the BOM, one with and one without a non-linear parallel loop. When the CPU applies a heavy output current transient to the system, the presence of the non-linear loop generates a better Vout regulation, with a smaller drop. In other words, it is possible to state that, keeping the same drop, non-linear loops allow one to use an output capacitor filter, much smaller.
However, non-linear loops come at a price.
The drawback of using a non-linear loop is that is it difficult to tune. The main difficulty is due to the fact that state-of-the-art CPUs have several power states; in full activity, the CPU has high current steps and slew rates, and in lower activity states, the current transient step and slew rate are medium and low.
The non-linear loop is tunable on one particular step of current and a particular slew rate.
If the device is tuned to trigger the non-linear loop at low to medium current steps, it will trigger too often, and the converter might end up unstable. This is not acceptable, so usually designers trigger for high current steps. What happens is that it becomes difficult to stay within electrical specifications at low power states, unless some of the output capacitors are put back, defeating the purpose that this technology is trying to achieve.
Figure 3, below, shows an example of such a case. The latest Intel CPUs have different electrical specifications for their supply voltage: at high activity (PS0), and at medium-low activity (PS1-2).
In PS1, the output current transient is much smaller. As stated above, the non-linear loop cannot be made sensitive to PS1 transients because, if so, the overall system would become unstable. Some of these smaller transients are then not sensed, resulting in Vout drop outs of electrical specifications for the controller. To compensate for this, the number of output capacitors has to be increased, cancelling the advantage of saving output capacitors that the non-linear loop was meant to provide.