Managing inrush and system protection for electrical systems

John Cummings, Texas Instruments -May 07, 2013

The methods of protecting electronics from circuitry failures and managing inrush current at power on has evolved significantly from a simple fuse and maybe a P-channel FET to much more sophisticated solutions. These highly integrated solutions manage the inrush into the system as well as have the ability to keep the pass element, which typically is a FET, in its safe operating area (SOA). This provides much better control and fault telemetry for system diagnostics. This article discusses enhanced solutions for system protection and key points of concern.


Simple system protection


The simplest form of protecting electrical circuits is a properly rated fuse. When digging into the proper solution for your application, there are a variety of fuses to choose from including, but not limited to fast blow, slow blow, poly, and smart fuse. The reason for the various types of fuses is because each one has its own issue.


Fast blow fuses are well named because they do exactly that. They blow quickly, which means there is a high potential for nuisance trips resulting in product returns. For this reason a better than 50% de-rating is essential for picking this type of fuse. This means a 5A rail should have a fuse rated higher than 10A to avoid false failures in the application.


Slow blow fuses take longer to open, but are still subject to nuisance trips. Here at least 50% de-rating typically is the recommendation.


Poly fuses have a nice feature in that if the fault clears, they will effectively heal, but at a small cost. With every trip, the subsequent trip point threshold is lower or easier to trip. Therefore, the probability of false tripping can increase over time.


Smart fuses or three terminal fuses are devices that can be blown on command, or as a result of an overcurrent event. Typically these are much more expensive than the above, and require that the supply voltage remain high enough to actually blow the fuse. Otherwise, in a fault everything can get very hot and may not result in a safe shutdown.


All four solutions have two major issues that can lead to nuisance trips. First, they have no means to limit the inrush current into the system at power up or after a brown out. Second, because of the de-rating required, they may allow enough current to pass in a system failure to allow the failed circuitry to heat to the point of a more severe failure. For example, a 5A-rated 12V system may try to use a 10A or higher rated fuse. In the event of a short with a good power supply, this may attempt to deliver up to 120W into the failed circuitry.


Inrush management


Most nuisance trips are the result of inrush currents. A low-cost means of minimizing inrush currents can be implemented with a P-Channel FET and a couple of resistors and capacitors (Figure 1).


Figure 1. Simple inrush management solution.


Of course, this circuit starts engaging the moment the input voltage is present. So it is common to hold of the circuit until an input power good signal is detected. Figure 2 shows one possible implementation using a window compactor to ensure that the 12V AC adapter is between 10.8 and 13.2V. As long as the a wide-supply voltage window comparator such as the TPS3700 sees that the adapter is within the valid voltage window, the power path via Q1 can be enabled.


Figure 2. Using the TPS3700 as a AC adapter detector.


While this may work for some designs, there are a few inherent issues with these schemes:


  1. Depending on the amount of load capacitance, both approaches may violate the FET’s safe operating area (SOA).
  2. Once enabled, there is nothing to limit the current into the load.
  3. If the load is shorted, the FET is likely to fail during startup. This may occur before the fuse and is best alleviated by using a FET that is rated for much higher power dissipation than required for the application and, therefore, a more expensive solution.


There must be a better way to protect the system at startup or in the event of a system level fault.


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