Design Con 2015

Product How-To: DC/DC converter family for space constrained designs

Ramesh Balasubramaniam, Director of Marketing, Enterprise Power, International Rectifier -June 18, 2013

Editor's Note: IR has managed a clever design that encompasses three key elements in a power management design, the switching regulator, the power MOSFET and the IC package itself. The goal of the designers was to address power designer's needs across a wide span of current output to the load ranging from 1A to 25A, while keeping a standard, scalable format for a flexible, efficient and robust design. They accomplished all of the above--read on:

The world is shrinking and all the electronic equipment with it. PCB real estate is at a premium as circuit functionality and density increases. The prime real estate is devoted to the core functionality of the application such as microprocessors, FPGAs, ASICs and their associated high speed data-paths and support components. The very necessary, yet unwanted, power supplies are forced to squeeze into the limited space left behind. Furthermore, as functionality and density increase, the power consumption must increase correspondingly. Of equal importance is the ease of design and robustness. This poses a challenge for power supply designers: how to supply more power in a smaller area while maintaining a common, easy design?

 

Addressing the issue of space, the answer, in theory, is simple: increase efficiency while, at the same time, increasing switching frequency. In practice for 12V systems, this is a very difficult problem to solve as higher efficiency and higher switching frequency can be considered mutually exclusive.

 

Complex applications typically require many power supplies to feed the multitude of subsystems and each has a slightly different requirement due to a variation in output voltage or output current. The converter design challenge is to find a common platform that is easily scalable across a wide current range whilst minimizing space, maximizing efficiency and providing industrial level robustness.

 

Nevertheless, this was precisely the task given to the Designers of IR’s 3rd generation Point-of-Load (POL) integrated voltage regulators. They are a family of DC-DC step-down Buck converters with integrated MOSFETs that address a wide current range from 1A to 25A.

 

The solution pulled together innovation in 3 areas: IC switching regulator circuit design, high efficiency MOSFETs and IC packaging. Firstly, to allow an increase in switching frequency to 1MHz and higher while still operating from a high input voltage such as 12V, a new patented modulator scheme that can create very small on-time pulses free of jitter was designed. For example, a 1MHz design that converts power from a 12V supply to a 1V output requires an 83ns pulse width and hence can tolerate very little jitter.

Standard PWM schemes commonly have about 30-40ns of jitter under these conditions which is unusable for this application. This is clearly illustrated in Figure 1a, where the jitter in a standard converter causes pulse skipping leading to excessive ripple. In contrast, Figure 1b, shows that the patented PWM modulator in a Gen 3 SupIRBuck® provides a clean, well controlled output ripple under the same conditions. The PWM modulator circuit within the Gen 3 SupIRBuck® family produces only 4ns of jitter, a reduction of 90% compared to standard solutions (figure 2). This has the dual benefit of reducing output voltage ripple by approximately 30% as well as allowing 1MHz or higher frequency/higher bandwidth operation for smaller size, better transient response and fewer output capacitors.

 

Figure 1: Output ripple for 1MHz, 16Vin  0.7Vout operation for (a) standard converter and (b) IR Gen 3 SupIRBuck

 

Figure 2: Jitter comparison

 

The new family integrates IR’s power MOSFETs and drives them with an internally generated 6.8V gate drive. This allows the Gen 3 SupIRBuck family, without any extra external circuitry, to obtain market-leading efficiencies (figure 3) over traditional solutions which are generally limited to a 5V gate drive.

 

Figure 3: Efficiency comparison for 5V and 6.8V gate drive

 

Standard packaging techniques to dissipate heat are sufficient for the low power current rails in the 1A-16A current range. However, for a high power rail such as 25A, to achieve market-leading thermal performance such as temperature rise as low as 50°C whilst delivering 25A, a proprietary package was utilized (figure 4). The synchronous MOSFET is flipped in a ‘source down” configuration while the control MOSFET remains in a traditional “drain down” configuration. The majority of the heat is generated in the source of the synchronous MOSFET and is thus conducted immediately out of the package and down into the ground plane rather than through the silicon die like competing solutions. The source of the control MOSFET is connected to the drain of the synchronous MOSFET by a single copper clip which is in turn connected to the switch node. This helps conduct the heat from the control MOSFET as well as providing an extremely low resistance electrical connection between the MOSFETs and the switch node.

 

Figure 4: Patented package maximizes thermal and electrical conduction for IR3847 (25A)

 


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