How to measure capacity versus bias voltage on MLCCs

Fons Janssen, Principal Member of Technical Staff, Maxim Integrated -January 12, 2015


High-capacity, multilayer ceramic capacitors (MLCC) have a property often not well understood by electronic designers: the capacitance of these devices varies with applied DC voltage. This phenomenon is present in all high-dielectric constant, or Class II capacitors (B/X5R R/X7R, and F/Y5V characteristic). However, the amount of variation can differ considerably among different MLCC types. A good article on this topic was written by Mark Fortunato.[1]

The conclusion of this article is that you should always check the capacitor’s datasheet to see how the capacitance varies with the bias voltage. But what if the datasheet does not include this information? How can you determine how much capacitance is lost under the conditions in your application?


Theory for Characterizing Capacitance versus Bias Voltage

A circuit to measure the DC bias characteristic is shown in Figure 1.



Figure 1. Circuit to characterize capacitance versus bias voltage.


This circuit is built around op amp, U1 (MAX4130). The op amp acts as a comparator, with feedback resistors R2 and R3 adding hysteresis. D1 sets a threshold above GND so that no negative supply voltage is needed. C1 and R1 form a feedback network to the negative input, which makes the circuit operate as an RC oscillator. Capacitor C1, the device under test (DUT), serves as the C in this RC oscillator; potentiometer R1 is the R.

The voltage waveforms of the op amp output pin, Vy, and the junction between R and C, Vx, are shown in Figure 2. When the output of the op amp is at 5V, capacitor C1 is charged by R1 until it reaches the upper threshold. This forces the output to 0V. Now the capacitor is discharged until Vx reaches the lower threshold, thus forcing the output back to 5V. This process repeats, resulting in a stable oscillation.




Figure 2. Oscillation voltages VX and VY.


The oscillation period depends on the values of R, C, and the upper and lower thresholds VUP and VLO:




Since 5V, VUP, and VLO are constant, then T1 and T2 are proportional to RC. (This is often referred to as the RC time constant.)

The threshold of the comparator is a function of Vy, R2, R3, and the forward voltage of D1 (VDIODE):




Where VUP is the threshold for Vy = 5V, and VLO is the threshold for Vy = 0V. With the given values these thresholds yield to approximately 0.55V for VLO, and 1.00V for VUP.

The circuit around Q1 and Q2 converts the cycle time into a proportional voltage. This works as follows. MOSFET Q1 is controlled by the output of U1. During T1, Q1 is on, clamping the voltage on C3 to GND. During T2, Q1 is off, allowing the constant current source (Q2, R5, R6, and R7) to linearly charge C3.[1] As T2 is increased, the voltage on C3 becomes higher. Figure 3 shows the voltage on C3 over three cycles.




Figure 3. C3 is clamped to GND during T1 and linearly charged during T2.


The average voltage on C3 (VC3) is equal to:




Since I, C3, α, and β are all constant, the average voltage on C3 is proportional to T2 and, therefore, also to C1.

Lowpass filter R8/C4 filters the signal while low-offset op amp U2 (MAX9620) buffers the output so that it can be measured with any voltmeter.

Before measurements can be made, this circuit requires a simple calibration. First the DUT is installed in the circuit, and VBIAS is set to 0.78V (the average of VLO and VUP) so the actual average (DC) voltage across the DUT is 0V. The output voltage will vary when potentiometer R1 is varied. Adjust R1 until the output voltage reads 1.00V. Under these conditions, the peak voltage on C3 is around 2.35V.[2] The bias voltage can be modified and the output voltage will show the resultant percentage change in the capacitance. For example, if the output voltage is 0.80V, the capacitance at that particular bias voltage is 80% of the capacitance at 0V bias.


[1] This will only be linear when using a capacitor with constant capacitance up to 5V bias voltage (MKS, MKT, etc).

[2] To prevent saturation of Q2, the voltage peak on the collector (= VC3) should stay below the emitter voltage minus the emitter-collector saturation voltage, which yields to approximately 4V.


Loading comments...

Write a Comment

To comment please Log In