PFC totem pole architecture and GaN combine for high power and efficiency

-June 14, 2017

The Open Compute Project (OCP) was begun by Facebook, in an effort to reduce OPEX and CAPEX of hyperscale data centers, by openly sharing data center solutions and building blocks between interested companies. Google joined the OCP in 2016 and Bel Power Solutions has been providing OCP-compliant power solutions since OCP began.

As cloud data centers begin to grow at a fast pace toward the anticipated fast growth of the IoT, 5G, smart home, smart cities, autonomous vehicle deployment, Google, Facebook, and other such companies are trying to squeeze as many racks of equipment as they can into these new cloud data centers. New solutions are emerging, especially in the power management arena. One such solution that caught my eye recently was Bel Power’s TET3000, a GaN-based, DSP-controlled, 3000W AC-DC, PFC-corrected, DC-DC power supply using Transphorm’s TPH3205WSB, 650V Cascode GaN FETs in the design.

I recently spoke to Transphorm’s COO, Primit Parikh, and Bel Power Solution’s CTO, Alain Chapuis, to get an in-depth technical view of the coordinated effort to develop a new power design architecture, in the TET3000—a GaN-based AC-DC power supply using a totem pole power factor correction topology.

Beyond Titanium

We discussed Titanium power supplies with 96% efficiency, which are needed here, but in the future we need to go beyond that with 48V solutions coming up soon.

A recent history of PFC topologies

I received a great history lesson in the recent evolution of power factor correction (PFC) from my discussion with Parikh and Chapuis. We started with a 98.2% efficiency in a classic PFC stage using a SiC diode bridge and Silicon switch architecture running in continuous current mode (CCM). There is a two-diode voltage drop loss in the SiC bridge with this design. Average EMC performance is seen due to limited ripple current (Figure 1).


Figure 1 A classical PFC stage (Image courtesy of Bel Power)

Next we moved on to an improved 98.8% efficient PFC design with an active bridge composed of Silicon power MOSFETs; this architecture helps to get rid of the bridge rectifier voltage drop losses by using this lower RDSON solution. The drawback is the need for higher-than-normal voltage FETs to handle voltage surges (Figure 2).

Figure 2 An improvement in the PFC stage with Silicon MOSFETS added (Image courtesy of Bel Power)

The 99% efficiency totem pole PFC stage design using Silicon MOSFETs and zero voltage switching (ZVS) was discussed as an improved next step. Here we still have high peak currents which lead to high conduction losses and the need for larger Silicon MOSFETs which limit this architecture in higher power capability. This type of design needs to operate in critical conduction mode since the high-side switch cannot be switched under load. Noise is a problem here, since we need filters for sawtooth waveforms; we lose efficiency here too. It would require a multi-phase approach to get power levels past 750W, but synchronization of the switching frequencies may lead to higher circulating currents. Bel Power demonstrated this architecture in 2011 (Figure 3).

Figure 3 An improved totem pole PFC stage (Image courtesy of Bel Power)


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