Low power design techniques

Editor's Note: Low power design continues to garner increased attention as product manufacturers find themselves facing market pressure to eke out maximum battery life in mobile applications and otherwise reduce power consumption in nearly every other application segment. In this excerpt from "Power Management in Mobile Devices," author Findlay Shearer, Senior Product Manager, Freescale Semiconductor, offers a review of low-power design techniques that should be in every engineer's toolkit.

Adapted from "Power Management in Mobile Devices" by Findlay Shearer (Newnes)

3.1 Low Power Design Techniques
Many design techniques have been developed to reduce power and by the judicious application of these techniques, systems are tuned for the best power/performance trade-offs.

3.1.1 Dynamic Process Temperature Compensation
A common engineering philosophy when designing a System-on-a-Chip (SoC) is to insure that they perform under “worst-case” conditions. Worst case in semiconductor manufacturing applies to very high temperatures and variations in the manufacturing process; transistor performance varies in a predefined range of parameters. Thus, some SoCs from the same wafer lot are capable of supporting higher operating frequencies (best case - fast process) or lower frequencies at the bottom of the predefined performance window (worst case - slow process) at the given voltage (Figure 3.1).

Dynamic process temperature compensation (DPTC) mechanism measures the frequency of a reference circuit that is dependent on the process speed and temperature. This reference circuit captures the product’s speed dependency on the process technology and existing operating temperature and lowers the voltage to the minimum level needed to support the existing required operating frequency (Figure 3.2).

A mobile device containing a fast-process SoC operating in a moderate climate condition can be expected to work at the worst-case calculated voltage to support the required frequency. This is less than an optimum energy savings.

The DPTC concept allows the supply voltage to be adjusted to match the process corner and SoC temperature. If the process corner is “best case” a lower supply voltage can be applied to support the required performance of the SoC. Similarly, the temperature of the part can be used to adjust the supply voltage.

The available performance is monitored by different types of reference circuits comprised of free-running ring oscillators. The inputs from reference “sense” circuits are processed by internal control and compare logic and written to software readable registers. If there is a significant (predefined) change in the reference circuit delay values, an interrupt is triggered. The relevant software interrupt routine calculates the new required voltage and re-programs the Power Management IC (PMIC) to supply the new voltage to the SoC. A new voltage is applied, based on the reference circuit delay, values change, providing feedback and closing the loop of the DPTC mechanism. This insures that the system stabilizes at the proper voltage level. Software control permits fast and simple changes.

DPTC can result in an approximate power savings of 35%, significantly improving the battery life.

3.1.2 Static Process Compensation
Static process compensation (SPC) follows a similar path to DPTC but without the temperature compensation aspect. SoCs are designed at the worst-case process corner (see Figure 3.1). However, production wafer lots are typically manufactured close to a typical point in the “box” and as a result can run at a lower voltage and still meet performance requirements.

SPC is a technique of identifying minimum operating voltage for each SoC at the production line and programming the fuses with the information. Software reads the fuses to set the operating voltage for the SoC.

The basic circuits required to support SPC are similar to those employed in DPTC and integrated into the SoC. They include a ring oscillator, support register, and fuses (Figure 3.3).

The frequency of the ring oscillator correlates with the process corner. The support register captures the oscillator frequency and the fuses are programmed to define the counter frequency and voltage for the SoC.

3.1.2.1 Compared to DPTC
SPC does not compensate voltage for temperature and the operating voltage is not changed dynamically in SPC. In addition, the SoC manufacturer can test the SoC to the SPC defined voltage. Given that SPC is a subset of DPTC, it has been demonstrated that the temperature compensation aspect of DPTC provides marginal benefit to energy conservation.