Design Con 2015

Equations and Impacts of Setup and Hold Time

Deepak Kumar Behera and Karthik Rao C.G., Freescale Semiconductor -August 10, 2012

Before getting into any relationships, impacts or equations, let’s first have a brief overview of what exactly is setup time and hold time.

Setup time is defined as the minimum amount of time BEFORE the clock’s active edge by which the data must be stable for it to be latched correctly. Any violation in this required time causes incorrect data to be captured and is known as a setup violation.

Hold time is defined as the minimum amount of time AFTER the clock’s active edge during which the data must be stable. Any violation in this required time causes incorrect data to be latched and is known as a hold violation.

For more information on the intra-flop aspects of setup and hold time, see reference [1].

Equations for Setup and Hold Time
Let’s first define clock-to-Q delay (Tclock-to-Q). In a positive edge triggered flip-flop, input signal is captured on the positive edge of the clock and corresponding output is generated after a small delay called the Tclock-to-Q. The flip flop can only do the job correctly if the data at its input does not change for some time before the clock edge (Tsetup) and some time after the clock edge (Thold). Again, the clock signal which circulates via clock tree throughout the design has its own variability termed as skew.

From Figure 1 below, we derive equations for setup time and hold time. Figure 1 shows two talking flops, the first being the launching flop and the second is obviously the capturing flop. We shall derive equation for setup time for the capturing flop and equation for hold time for the launching flop. However, the derived equations will be true for either of the flops or for that matter any flops in the design.


Figure 1. Two Talking Flops Scenario

In the diagram above, at time zero FF1 is to process D2 and FF2 is to process D1. Time taken for the data D2 to propagate to FF2, counting from the clock edge at FF1, is invariably = Tc2q+Tcomb and for FF2 to successfully latch it, this D2 has to be maintained at D of FF2 for Tsetup time before the clock tree sends the next positive edge of the clock to FF2. Hence to fulfill the setup time requirement, the equation should be like the following.

Tc2q + Tcomb + Tsetup Tclk + Tskew ------- (1)

Let’s have a look at the timing diagram below to have a better understanding of the setup and hold time.


Figure 2. Setup and Hold Timing Diagram

Now, to avoid the hold violation at the launching flop, the data should remain stable for some time (Thold) after the clock edge. The equation to be satisfied to avoid hold violation looks somewhat like below:

Tc2q + Tcomb Thold + Tskew ------- (2)

As seen from the above two equations, it can be easily judged that positive skew is good for setup but bad for hold. The only region where the input can vary is the ‘valid input window’ as shown in Figure 3.


Figure 3. Valid Input Window




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