Designing low-energy embedded systems from silicon to software

-November 28, 2012

Low-energy system design requires attention to nontraditional factors ranging from the silicon process technology to the software that runs on microcontroller-based embedded platforms. Closer examination at the system level reveals three key parameters that determine the energy efficiency of a microcontroller: active-mode power consumption; standby power consumption; and the duty cycle, which determines the ratio of time spent in either state and is itself determined by the behavior of the software.

A low-energy standby state can make an MCU seem extremely energy efficient, but its true performance is evident only after taking into account all of the factors governing active power consumption. For this and other reasons, trade-offs among process technology, IC architecture, and software construction are some of the many decisions with subtle and sometimes unexpected outcomes. The manner in which functional blocks on an MCU are combined has a dramatic impact on overall energy efficiency. Even seemingly small and subtle changes to the hardware implementation can result in large swings in overall energy consumption over a system’s lifetime.

Low-energy applications

Metering and alarm systems, for example, are often powered for 10 years by a single battery. A small increase in current consumption for a sensor reading (of which hundreds of millions may occur over the lifetime of the product) can result in years being lost from the product’s actual in-field lifetime. A simple smoke alarm that detects the presence of smoke particles in the air once a second will take 315 million readings during its life span.

The activity ratio or duty cycle of a simple smoke alarm is relatively low. Each sensor reading may take no more than a few hundred microseconds to complete, and much of that time is spent in calibration and settling as the MCU wakes up the ADCs and other sensitive analog elements and lets them reach a stable point of operation. In this case, the duty cycle is likely to lead to a design that is inactive approximately 99.98% of the time.

A traditional smoke alarm is comparatively simple. Consider a more complex RF design in which a sensor mesh relays results to a host application. The sensor needs to listen for activity from a master node so that it can either signal that it is still present within the mesh network or provide recently captured information to the router. This increased activity, however, may not affect the overall duty cycle; instead, more functions may be performed during each activation period using a higher-performance device. Because of its increased processing speed, made possible by a more advanced architecture and semiconductor technology, the faster device can provide greater energy efficiency than can a slower device running for more cycles. The key lies in understanding the interactions among process technology, MCU architecture, and software implementation.

Silicon choices

CMOS energy profile. Nearly all MCUs are implemented using a CMOS technology (Figure 1). The power consumption of any active logic circuitry is given by the formula CV²f, where C is the total capacitance of the switching circuit paths within the device, V is the supply voltage, and f is the operating frequency. The voltage and capacitance are factors of the underlying process technology. Over the past three decades, the on-chip operating voltage of CMOS logic has fallen from 12V to less than 2V as transistors have scaled down in size. Because voltage is a quadratic function in the active-power equation, the use of lower voltages has a significant impact.

Figure 1 Switching losses of a CMOS logic structure involve charging (a) and discharging (b) a capacitive load.

Although the capacitance term is linear, Moore’s Law scaling greatly assists in the factors that lead to reductions in its overall level. For a given logical function, a more recent process will offer lower capacitance—and, with it, lower power consumption—than its predecessors. In addition, advanced design techniques enable clock gating, which makes it possible to reduce the overall switching frequency by operating only those circuits with actual work to perform.

Compared with other technologies, CMOS dramatically reduces wasted energy; however, leakage current remains. In contrast to active power consumption, the leakage increases with Moore’s Law scaling and must be taken into account in any low-energy application because of the proportion of time that a low-duty-cycle system is inactive. As with active power consumption, however, circuit design has a dramatic impact on real-world leakage. Analogous to clock gating, power gating can greatly ameliorate the effects of leakage and make more advanced process nodes better choices for low-duty-cycle systems, even though an older process technology may offer a lower theoretical leakage figure.

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