Optimizing efficiency and flexibility in DSP systems
For as long as multipliers have been implemented in silicon, DSP (digital signal processing) devices have been developed to solve problems in audio, video, communications and a variety of other applications. In many cases the DSP algorithms have been implemented directly in dedicated customized logic to achieve an optimal solution. In others, generic programmable DSPs have been utilized to provide a flexible platform to implement algorithms in firmware. Increasingly, GPPs (general purpose processors) and CPUs (central processing units) have acquired capabilities to realize DSP algorithms, offering a platform to mix non-DSP functions like network stacks with complex DSP algorithms on the same CPU.
This article will explore the tradeoffs leading designers to these different design choices. Typically, well understood algorithms of limited complexity are implemented in dedicated hardware, whereas less rigid complex algorithms requiring multiple algorithm steps are implemented on programmable DSPs. If the application requires non-DSP algorithms, such as USB or network protocols, the choice becomes between a GPP and a DSP, where the ratio of DSP calculations to generic (e.g. protocol) computation will typically determine the outcome.
When considering the basic architecture of a DSP system, the fundamental question is whether to include a programmable DSP or not. As illustrated in Figure 1, dedicated hardware can be the most efficient but may suffer from lack of flexibility, whereas a GPP will offer the highest level of flexibility but may be the least efficient solution. Often the answer is obvious because of flexibility requirements or simply because of system components that cannot be effectively implemented in hardware, e.g. network stacks. In some cases, strict limits on power consumption may preclude a programmable approach. But when the answer is not so clear, the system architect will need to sketch out two separate architectures, with and without a programmable DSP, and rate the outcome against the key design criteria – cost, power consumption and schedule.
With increasing levels of integration, a programmable processor becomes the preferred choice. Although a DSP or CPU core figures prominently on functional block diagrams, the core itself typically occupies a very small area on a chip, typically corresponding to a few 10 KB memory blocks. And in many cases the law of “conservation of memory” pertains, namely that the same amount of data memory is needed independent of whether the system is implemented in fixed logic or programmable.
The following will focus on a mixed system with a programmable processor in which the design choice is more about how much dedicated logic should be included. The more that is pushed towards the programmable processor, the more complex and costly that subsystem becomes.
Figure 1. Tradeoff between efficiency and flexibility