Underlying technologies for non-volatile memories

Dr. Saied Tehrani, Spansion -January 14, 2013

The non-volatile memory market is growing rapidly with the continuous evolution of Flash technology to smaller geometries delivering higher density and lower cost per bit. At the same time, the convergence of improved intelligence, connectivity and intuitive interfaces is driving new applications and continuous market growth for non-volatile memories.

Non-volatile memory applications can be divided into standalone and embedded system solutions. Standalone applications tend to be driven primarily by costs and the constant need for next generation products. And while cost is also important in embedded solutions, longevity, expanded functionality (extended temperature ranges, higher reliability, higher performance, low power, etc.), and support are required for embedded systems. The embedded market relies mainly on NOR Flash for critical applications such as code storage due to its reliability and performance while NAND is typically utilized for less critical data storage.

In recent years, NAND technology has been scaling more aggressively than NOR and is facing greater challenges in scaling to smaller geometries. Therefore, the industry is evaluating a number of exploratory technologies with the aim of achieving scalability for higher densities and reduced costs at acceptable levels of performance and reliability.

Hitting the Limits with Floating Gate NAND
While the industry has found ways to push NAND scalability, it’s looking extremely challenging for the industry to scale at the same pace beyond 20 nm using current Floating Gate technology.

The main challenge in scaling in Floating Gate technology is the reduction in spacing between neighboring cells. The smaller spacing makes it difficult to fill the necessary interlay dielectric and control gates between the neighboring Floating Gate cells. The close proximity of the cells also significantly increases the capacitive coupling causing neighbor cell disturb.

Charge Trap and Three-Dimensional (3D) NAND
In order to continue to scale NAND Flash, the industry is evaluating two possible ways to scale below the 20 nm level: 1) Three-Dimensional cell; and 2) planar cell, such as Charge Trap NAND.

3D Flash technology takes a “stacking” approach. One can look at it as if the technology layers are stacked, like a high rise building each floor representative of a different memory cell. The challenge with this technology is that you have very tall “stacks” with a very high aspect ratio (height over width) which creates processing challenges in uniform patterning and depositing materials. In addition, the high aspect ratio of the stacked cell structure makes it less mechanically stable.

Planar Charge Trap NAND technology differs from the more conventional Floating Gate technology in that it uses a very thin layer of silicon nitride film, around 100 angstrom (A), to store electrons rather than the over 1000 A of a typical Floating Gate storage layer. The thinner layer of silicon nitride significantly reduces the neighboring cell capacitive coupling and eliminates the challenge of filling interlay dielectric in narrow and high aspect ratio spaces between the Floating Gates.

Figure 1. Planar Charge Trap NAND Architecture.

Next: Title-1

Loading comments...

Write a Comment

To comment please Log In