The 2013 DesignVision winners announced at DesignCon
Integrating and testing IP blocks in large SoCs has always been a manual, time-consuming effort. The IEEE P1687 (“IJTAG”) (http://www.techonline.com/electrical-engineers/education-training/tech-papers/4394678/IEEE-P1687-Internal-JTAG-IJTAG-Tutorial) standard was created to solve this problem.
Mentor Graphics’ Tessent IJTAG product, announced in October of 2012, won in this category because it provides comprehensive support for the IJTAG standard by automating the integration of test facilities and other instrumentation into their complex SoC designs.
The IJTAG standard itself creates an environment for plug-and-play integration of IP, including control of boundary scan, built-in self-test (BIST), internal scan chains, and debug and monitoring features in IP blocks. The standard also defines hardware rules related to instrumentation interfaces and connectivity between these interfaces, a language to describe these interfaces and connectivity, and a language to define operations to be applied to individual IP blocks.
The Tessent IJTAG tool reads IJTAG files and validates that the components are properly connected to the top-level access point. It then retargets IP-level procedural descriptions to the top-level and translates the results into Verilog test bench language and standard test vector formats like WGL, STIL or SVF. With the tool, designers can automate the process of connecting the test access ports and reusing the test patterns of any P1687-compliant IP block, producing a hierarchical network with a single top-level interface to test an entire SoC. The tool also supports testing, monitoring, and debug where pin count is limited or test I/O is difficult, as in 3D die configurations.
Tessent IJTAG lets IP suppliers and SoC integrators replace ad hoc and custom solutions with plug-and-play automation. This saves engineering time, and significantly reduces the length of an aggregated test sequence for all the IP blocks in an SOC. This translates directly into reduced test time and smaller tester memory requirements.