Design Con 2015

Multi-level-cell PCMs last for 10 million cycles, Part 1

-July 26, 2013

In this follow-up to the International Memory Workshop (May 26-29, 2013; Monterey, CA), phase-change memory expert Ron Neale has analyzed some of the work presented by IBM, interviewed the lead author Haris Pozidis, Manager of Memory and Probe Technologies at IBM Research, Zurich - and drawn some conclusions of his own.

This year’s International Memory Workshop was dominated by papers on developments in flash memory, resistive RAM and magnetoresistive RAM, with just three papers on phase change memory (PCM). The eagerly awaited PCM paper from IBM [1] updated conference attendees on the further progress that company has made on their multi-level cell PCM (MLC-PCM) drift-level adaption (DLA) technique. The IBM work pulled together a number of important development threads: cell structure, drift-compensation and write-erase lifetime, with the number of devices evaluated negating any of the criticisms of the past where elsewhere many workers claimed optimistic results from the evaluation of too few devices.

For this writer, compared with elsewhere, the IBM paper provided a refreshing level of honesty in addressing PCM problem areas, especially in relation to wear out and element separation with write/erase lifetime. The IBM paper suggested that progress will only be made in solving the crucial reliability problems of today's memory by an effort that coordinates device and structural engineering, electrical sensing techniques and signal-processing technology (applicable to all memory types not just PCM). To this, they might have added that the removal of the lithographic scaling roadblock that faces PCM at around sub-20-nm is only likely to be solved in the short term for bit density per package by a multi-level cell multi-chip package (MLC-MCP) solution.

The new results reported addressed the reliability of IBM's drift compensation technique with write/erase lifetime, or endurance cycling. Those results indicated that after 106 write/erase cycles of a 64-kcell block it was possible to achieve error rates lower than achievable by other methods of compensating for drift.

Drift-tolerant methodology
Before reviewing the new results a quick and simplified reminder of how the drift correction technique works might be in order. Although drift is one of the many problems now receiving the attention of those trying to develop competitive PCM devices, it is not a new problem. In the case of single-bit memory, resistance drift towards higher values would tend to improve the situation in relation to the read operation, so it was not a first order problem; providing, that is, that any drift did not compromise the write by increasing threshold voltage levels.

Drift is caused by relaxation of amorphous materials (similar to the stress in rapidly cooled glasses) and reveals itself as increases in resistance. It’s a very unwelcome effect, even more so in multi-level memory cells, for which resistance is the measure of the logic state(s) of the memory cell.

Two very beneficial facts have been discovered in relation to drift, much of it detailed by IBM work on MLC memory cells. The first is that when a given memory cell is written to its different resistance levels, the relative values of the increases in resistance for each level, with drift and time, remain constant (see figure 1). The second is that the statistical value of the resistance is Gaussian like and expands as the resistance increases.


Figure 1. The family of curves for a multi-level PCM cell show drift in resistance values with time while the relative values remain constant.

The IBM DLA method uses a mixture of signal processing and in addition more conventional error correction and detection methods. The levels must first be estimated and then finally positioned as accurately as possible.

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