The problem with memory test
First, there is the disappearance of test pads on circuit boards to enable design debug with oscilloscopes and logic analyzers in design, and, in manufacturing, bed-of-nail fixtures for in-circuit test (ICT), manufacturing defect analyzers and flying probe systems. Second, there are the restrictions on placing any sort of a test probe on high-speed memory buses because of the capacitive signal distortion created by the probe. Third, memory bus protocols are becoming increasingly complex. And, finally, there are a host of other factors, including manufacturing process variations.
Fortunately, a number of non-intrusive board test (NBT) or probe-less methods for testing memory, including boundary-scan test (BST), functional test, processor-based testing methodologies such as processor-controlled test (PCT), FPGA-based testing mechanisms such as FPGA-controlled test (FCT) and embedded memory built-in self-test (memory BIST) can be deployed without relying on probes or test pads on circuit boards. Each method has its advantages and disadvantages. Implementing any one method will involve tradeoffs. Deploying several can deliver the debug and test coverage no longer possible with legacy methods. This is the first of a three-part series of articles that will describe these various non-intrusive debug and test methods and explain some of the most salient tradeoffs. In particular, some of the complexities involved with testing the high-speed DDR (double data rate) memory bus will be explained.
>>Read Part 1: The problem with memory test directly on www.tmworld.com
>>Read Part 2: Part 2: A review of non-intrusive debug and test methods based on embedded instruments and how these methods can meet the challenges that design and manufacturing engineers are encountering.