Design Con 2015

Signal integrity issues on the rise

-January 22, 2013

Electronics design trends that ratchet up design complexity and speed, such as the use of multiple high-speed buses, bring new signal-integrity challenges. With that in mind, EDN assembled a virtual panel of engineers working in signal integrity to examine the current impairments, assess how well the available test equipment is measuring up, and determine what we can do both short- and long-term to improve signal integrity. Admittedly, there are many things that can affect signal integrity (Reference 1); in this discussion, we focus primarily on crosstalk and EMI.

What’s the problem?

Many a trained eye is focused on the effects of multiple high-speed buses on signal integrity and how to avoid the related problems. Chris Loberg, senior technical marketing manager at Tektronix Inc, and Tim Caffee, vice president for design validation and test at Asset InterTech Inc, agree that shrinking operating margins on high-speed buses are contributing to the challenges.

“The design trend is faster serial speeds, above 10 Gbits/sec, with no new cost-effective architecture for improving signal-path accommodation of issues like EMI and crosstalk,” Loberg observes. “So, signaling accommodations like equalization must be made to minimize EMI and crosstalk effects, enabling the receiver to accurately determine the serial-bus logic transition.”

Loberg notes that interval times—the time between a transition to one or zero—are shrinking; as a result, in a traditional eye diagram Image: Shutterstock used to evaluate transitions, EMI and crosstalk are “closing” the eye. Engineers can no longer effectively evaluate signal integrity, as crossing points and timing-integrity evaluations become much more challenging.

Caffee notes that with each successive generation of high-speed bus, operating margins are gradually shrinking as signal frequencies increase, enabling effects such as jitter, intersymbol interference (ISI), and crosstalk to “create havoc” on the signal integrity of high-speed SerDes and memory channels. Each new step to a higher speed and signaling frequency makes the bus more susceptible to distortions and anomalies that can effectively disrupt traffic and stall system throughput.

The eye diagram in Figure 1 illustrates this point, showing the effects of increasing signal frequencies on three generations of a hypothetical high-speed bus and the resultant, decreasing operating margins on the bus. As frequencies increase, even the slightest distortion can disrupt signaling throughput.


Figure 1 Moving from 6 (broken line) to 8 (dotted line) and, eventually, 10 Gbits/sec (solid line) closes the eye around the operational sweet spot at the center of the diagram (courtesy Asset InterTech).

Alan Blankman, product manager for signal-integrity products at Teledyne LeCroy, agrees that higher bit rates (>25 Gbits/sec) and “parallelized serial” standards such as PCI Express (PCIe), 40/100GBase-R, and InfiniBand are contributing to signal-integrity issues. “Faster bit rates require faster edges with higher-frequency content, which results in bigger reflections due to impedance mismatches at connectors, vias, packages, etc.; higher levels of loss; and higher levels of crosstalk and EMI, due to increased coupling to neighboring traces,” Blankman says.

Figure 2 The Agilent U4154A logic analyzer uses its eye-scan capability to place the sampling point automatically in both time and voltage within the eye, making measurements on eye openings as small as 100 psec × 100 mV.
Shamree Howard, signal-integrity program manager at Agilent Technologies, adds that faster speeds create issues for accurate data capture, requiring precise triggering. She says jitter measurements are the key to characterizing high-speed digital links, noting, “The measurement of jitter—even if the user is provided a one-button interface—is a sophisticated affair, taking into account clock recovery and knowledge of phase-locked loops, jitter decomposition techniques and assumptions for them, crosstalk and its effects, and waveform statistics that require different approaches” (Reference 2). Howard adds that the Agilent U4154A 4-Gbit/sec AXIe logic-analyzer module can make reliable measurements on eye openings as small as 100 psec × 100 mV (Figure 2).

Howard Johnson of Signal Consulting Inc concurs that circuits at very high speeds are notoriously difficult to probe. “Even in cases when a probe exists that can do the job, you often cannot place the probe at the point in a circuit that you wish to observe,” says Johnson. He suggests that the answer is to use cosimulation, or the process of simultaneously developing both a physical circuit and a software simulation of it.

The problem, observes Ransom Stephens of Ransom’s Notes, is that, despite new oscilloscope techniques from leading manufacturers, there is no automated way to identify crosstalk unambiguously. The latest test products offer ways to estimate the effect of crosstalk on the bit error rate (BER), but they are all process-of-elimination approaches.

“Avoiding crosstalk is simple in principle but sometimes impossible in practice,” Stephens acknowledges. Because crosstalk is caused by jolts of radiation when an aggressor signal makes a logic transition, increasing the rise/fall times will reduce crosstalk. Because it’s interference, increasing trace separation has a big effect, too.

“I think that careful differential design is your best bet, though,” Stephens offers. “If you can get the differential skew really small and get the two traces nearly on top of each other, then the cancellation from differential signaling has a fighting chance.”


Loading comments...

Write a Comment

To comment please Log In