Design Con 2015

Understand and perform testing for MIPI M-PHY compliance

Chris Loberg -February 19, 2013

As MIPI Alliance standards gain increasing acceptance in the world of mobile device design, engineers need to become proficient at electrical PHY layer compliance testing for the higher speed M-PHY serial interconnects. A full set of tests spanning both the transmitter and the receiver are required to validate designs – a task that is made tougher as speeds and complexity increase.  Understanding how to setup and perform critical verification and debug tests is critical to any successful M-PHY development effort.

MIPI Technologies Overview

MIPI provides specifications for standard hardware and software interfaces within a mobile device. MIPI specifications improve interoperability between components from different component vendors, reduce the effort of integration and speed up the time-to-market for mobile devices.
One of the primary roles of MIPI standards is to convert legacy parallel interfaces into modern serial data interfaces for scalable, more efficient mobile device designs. As a result, all MIPI standards are serial data and follow a set of protocol stacks. Figure 1 shows an overview of application areas in a mobile design against the applicable MIPI protocol layer standards.


Figure 1. MIPI standards support multiple application areas.

The physical layer standards include D-PHY, M-PHY, SlimBus, HSI, and DigRF 3G. The two PHY layers, D-PHY and M-PHY, are expected to coexist for a long time. Both are reusable, scalable physical layers for the various components on a mobile terminal.

First out of the chute, D-PHY differs significantly from many existing mobile interfaces because it can switch between the differential high-speed (HS) and the single-ended low-power (LP) modes in real time depending on the need to transfer large amounts of data or to conserve power to prolong the battery life. The D-PHY interface supports simplex or duplex configurations with a single data lane or multiple data lanes. The clock is always master to slave and in quadrature phase with data.

Even though D-PHY is a capable interface, since it is synchronous, speed is limited to 1.5 Gbps, preventing it from supporting applications that require higher data transfer rates. That’s where M-PHY, approved in late 2010, comes in. It is a much more powerful PHY designed to handle the ever-increasing data bandwidth requirement of mobile devices.

M-PHY offers asynchronous data rates exceeding 5 Gbps, giving designers the ability to speed up memory transfer and CSI/DSI interface speeds. In addition to higher speeds, the M-PHY uses fewer signal wires because the clock signal is embedded with the data through the use of 8b/10b encoding. M-PHY is optical friendly. As shown in Figure 2, M-PHY is used as physical layer for a number of other interfaces including DigRF v4, LLI, SSIC and UniPro.


Figure 2. M-PHY is used as the physical layer for a number of other interfaces.

M-PHY data transfers occur in burst or in continuous mode and can be in high speed (HS) or low speed (LS).  M-PHY supports two drive strengths, large amplitude (LA) and small amplitude (SA). M-PHY supports two types of modules: Type-I and Type-II based on signaling scheme used in low speed mode. Low speed mode can use either pulse width modulation (PWM) or non-return to zero (NRZ) as signaling schemes.

M-PHY Transmitter Testing
The M-PHY specification outlines a comprehensive group of tests designed to verify the various transmitter signaling and timing requirements of M-PHY transceivers. HS mode is used in both Type-I and Type-II modules, which means that the tests related to HS mode are required for all modules. Due to the faster signaling frequency, a number of performance parameters need to be measured on HS mode signals including slew rate, transition time, pulse width, unit interval, differential DC and common mode voltage, minimum eye opening, power spectral density (PSD) and jitter (long term and short term). With the exception of PSD, the other high-speed-mode parameters are either related to time or voltage and can be measured easily using an oscilloscope. While an oscilloscope can be used for PSD, it requires a unique process that will be detailed later in this article.

In M-PHY HS measurements, signal validation is done on each acquisition. As part of signal validation, the following parameters are checked and validated on the acquired signal:

•    Data Rate: The unit interval of an M-PHY burst data signal needs to be computed since data rate variations could be within 2,000 ppm for any HS gear.
•    MARKER0: This parameter (considering both positive and negative disparity) is searched in the acquired waveform. If MARKER0 is present, then the signal validation is passed for this parameter.

M-PHY data transmissions can happen in burst or continuous mode. In burst mode, data will have different states including PREPARE, SYNC, MK0, PAYLOAD and STALL. M-PHY has a number of electrical parameters that need to be measured at specific states of the burst. For example, PREPARE length uses PREPARE state, differential DC positive and negative uses PREPARE and STALL respectively. EYE, jitter, transition time and unit interval use MK0, PAYLOAD and MK2 only. From a test perspective, this means the engineer has to identify different states in a burst waveform, place markers or cursors and then measure the required electrical parameter.

M-PHY burst has SYNC and PAYLOAD which are 8b10b encoded, meaning there are no symbols that have more than five continuous ones or zeros (maximum allowed run length of 5 bits). This behavior is used to identify PREPARE and STALL. The remaining part of the waveform (SYNC, MK0, PAYLOAD and MK2) are converted into bits, the location of MK0 (considering both positive and negative disparity) and end of burst are identified and measurements are performed on cursor gated regions.

PSD Measurements

The M-PHY bus is also used as a physical layer in DigRFv4 for communicating between baseband and radio frequency ICs. The bit transfer rates of M-PHY are high enough to support the operating bands of the radios in mobile systems. Electromagnetic interference (EMI) radiating from the serial interface can interfere with the mobile device’s radio low noise amplifier. Research has shown that the common-mode signal component dominates EMI interference. Therefore, as part of M-PHY transmitter compliance testing, designers need to ensure that the PSD of the common mode signal is within the mask defined by the following:


Usually PSD is computed using a spectrum analyzer, which means that both an oscilloscope and a spectrum analyzer would be needed to complete M-PHY transmitter tests. Since all the other tests are completed using an oscilloscope, a better solution is to have the option of performing PSD with an oscilloscope. While computing PSD using an oscilloscope is a challenge, it can be accomplished as follows:
•    TxDp and TxDn signals are given as inputs to the oscilloscope
•    The common mode signal is computed using the oscilloscope’s math function
•    The common mode signal is passed through a hamming window
•    The FFT of the windowed common mode signal is computed using the oscilloscope’s FFT function
•    An average of the spectral magnitude of N acquisitions is computed. Let this average result be “X”
•    PSD in dBm/Hz is computed using the following:

where
R = 25 Ohm, the common mode resistance
RBW = Resolution Band Width = 1.3/ (Gating Duration) (Factor of 1.3 is due to the hamming window)
Factor of 1,000 is to convert dB to dBm
•    Minimum PSD margin is computed as, PSDMargin = Minimum (CMmask – PSD)
•    If minimum PSD margin is greater than zero, then the PSD of a common mode signal is considered to be within EMI limits.

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