Verification and debugging techniques for next-generation DDR
The trends in the new memory specs are predictable: higher speeds, increased densities, smaller packaging, and reduced power consumptions. For design engineers charged with electrical verification and debugging, the new standards bring a number of notable changes and new measurement challenges. The combination of faster speeds and lower voltage means that signal integrity is more important than ever, while denser packaging will create signal access challenges.
This article highlights the changes these new standards bring to electrical verification and describes how to prepare for proper signal access to LPDDR3 and DDR4 memory systems. It will also look at instrument selection and techniques needed for performing electrical verification tests on these emerging standards.
In May of 2012, JEDEC published the JESD209-3 Low Power Memory Device Standard. In comparison to LPDDR2, LPDDR3 offers a higher data rate, greater bandwidth and power efficiency, and higher memory density. LPDDR3 achieves a data rate of 1600 MT/s and uses a number of new technologies, including write-leveling and command/address training, optional on-die termination (ODT), and low-I/O capacitance.
As with LPDDR2, LPDDR3 supports both package-on-package and discrete packaging types to meet the requirements of various mobile devices, and it offers designers the ability to select the options that best meet the needs of their product. LPDDR3 preserves the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management.
From an electrical verification perspective, LPDDR3 is pushing the system power envelope with its combination of lower operating voltage and higher bandwidths. By comparison, first-generation LPDDR ran at 200 MHz at 1.8V. With LPDDR2 voltage dropped to 1.2V while speed increased to 533 MHz. Now LPDDR3 calls for the same 1.2V but runs at 800 MHz. This means that signal integrity will be an important factor in order to verify clock cycles on shorter 1.25 ns clock periods. Table 1 shows a comparison between the two generations, indicating the need for higher bandwidth oscilloscopes to maintain signal integrity.
Released in September of 2012, the DDR4 specification calls for greater performance, significantly increased packaging density, improved reliability and lower power consumption compared to DDR3. As shown in Table 2, voltages drop to 1.2V from 1.5V to reduce power consumption while the performance factor nearly doubles to 3,200 MT/sec. (megatransfers per second). Other changes include higher densities to support memory-intensive server applications, higher data rates and the ability to stack pins for higher density module placement.
From a test perspective, as with LPDDRR3, the move to higher transfer rates and lower voltages will increase the emphasis on signal integrity and timing and margin measurements for validating memory technologies. To accommodate the increased measurement complexity, JEDEC is making a number of changes and updates to required test methodology.
One of the most significant changes is the proposed requirement to establish the reference voltage or V center used for compliance testing using a variable approach. For DDR3, this value was fixed at 750 mV. The new approach involves making multiple acquisitions of the output data (DQ) and a data strobe signal (DQS) Write burst. The largest to smallest voltage value for each is then measured and an average created using a simple formula. This then becomes the DQ voltage reference for centering and making reference measurements using an eye diagram. This process is shown in Figure 1.
Another notable change in DDR4 testing is the expanded use of eye diagrams. The proposed test specification will set required eye height and width and will provide guidance on what will be considered a deterministic level of performance from a timing perspective. It will also set margin requirements with random or Gaussian noise applied to the measurement. Figure 2 shows the eye diagram for DQ from the DD4 spec with recommended mask sizing that is placed on the Vref center.
Following the lead of many serial standards, DDR4 will now incorporate a statistical jitter measurement approach for speeds greater than 2133. For speeds under 2133, all jitter will be assumed to be deterministic jitter (DJ). For 2133 and above, tests will look at both DJ and random jitter (RJ). To date, many of the timing parameters for jitter have not been published, but designers should be aware that jitter testing will be a requirement. One benefit of expanded jitter testing in DDR4 is that should devices fail to meet jitter requirements, the test and measurement vendor community offers robust jitter decomposition tools that can help isolate the source of problems.
In addition, JEDEC will no longer require de-rating of pass/fail limits for setup and hold measurement based on signal slew rate, as was the case with DDR2 and DDR3. In discussing the issue with engineers, the JEDEC standards committee found that the complex de-rating procedure was poorly understood and rarely performed. Typically, most engineers relied on making standard slew rate measurements. In DDR4, this has been replaced with the Vref averaging and eye-mask measurements described above.