Ensure FinFET defect coverage with cell-aware test
The process of generating test patterns for digital circuits, typically referred to as automatic test pattern generation (ATPG), has been in use for decades. The approach is based on modeling circuit defects to a level of abstraction that enables a computationally efficient test-pattern generation process. For years, the simple stuck-at fault model was used. As circuits grew in performance and complexity, new fault models were gradually introduced and adopted to account for the growing probability of more complex defect types. Some of the most common of these include transition, bridging, open, and small-delay faults.
As the industry moves to increasingly smaller geometries, we have discovered that all of these fault models and associated test patterns are becoming less effective for ensuring desired quality levels. The reason for this is that all of the existing fault models only consider faults on cell inputs and outputs, and on the interconnect lines between these cells. In other words, only faults abstracted to the netlist level have been explicitly considered. It turns out, however, that a growing number of defects occur within the cell structures. TSMC has stated, “…for 90nm and beyond, a significant number of manufacturing defects and systematic yield limiters lie inside library cells.” With more recent fabrication technologies, the population of defects occurring within cells is significant, perhaps amounting to roughly 50% of all defects.
A new methodology that targets defects within cells was recently developed to address this coverage gap. This cell-aware test approach targets specific shorts and opens internal to each cell. Each cell is modeled at the transistor level, and analog simulations are performed to characterize the effects of these potential short and open defects. Based on the analog simulation results, a cell-aware model is created that directs ATPG to generate patterns targeting these internal cell defects.
The first step in the cell-aware methodology is to characterize each cell in a technology library. The flow is illustrated in Figure 1. The transistor layout for each cell, typically in GDSII format, is required as a starting point. An extraction tool, such as Calibre xRC, is used to extract a transistor-level analog netlist, including parasitic capacitors and resistors, which are used to identify the location of possible bridge and open defects, respectively. To model a potential cell internal bridge, then, the parasitic capacitor is replaced by a resistor model. Opens occur when there is a gap in a connection. In this case, a parasitic resistor that describes connectivity is replaced by a high-impedance resistor.
The final process in cell-aware characterization is to convert the list of input combinations into a set of the necessary input values for each fault within each cell. Because this fault information is defined at the cell inputs as logic values, it is basically a logic fault model representation of the analog defect simulation. This set of stimulus for each cell represents the cell-aware fault model file for ATPG.
Within this file, a simulated defect (now a fault) can have one or more input combinations. An example is shown in Figure 2. For this example fault ‘my_stuck_01’, ATPG will try to find any of the three input combinations when targeting this fault in a design. If any one of the combinations can be applied to an instance of the cell and the fault effect can be propagated to an observation point, then the fault is marked as detected for this instance; the other combinations are no longer necessary.
Because the cell characterization process is performed for all cells within a technology library, any design using that technology can read in the same cell-aware fault model file. Characterization only needs to occur once, and can then be applied to any design on that technology node.