Analyze high-speed interconnects

-July 23, 2013

Signal integrity (SI) addresses two key aspects in high-speed digital designs: signal timing and quality. SI analysis aims to ensure signals reach their destination in good condition. In a system, signals travel through various kinds of interconnections (e.g., from chip to package, package to RF board trace and trace to high-speed connectors), with any electrical impact happening at the source end, along the transmission path or at the receiving end, which affects both signal timing and quality. Connector performance directly affects system performance and reliability. As a result, designing and modeling connectors for multi-gigabit applications is one of the greatest challenges in high-speed digital applications.

When designing high-speed applications, signal transmission quality is a critical factor. At gigabit speeds, high-speed interconnects must be characterized along with the RF board traces. Ever-increasing demand for cleaner signal transmission means that maintaining good signal quality throughout the high-speed interconnects is crucial. Modern high-speed, multi-pin connectors are required to enable data transmission in systems at a very high rate (~ 5 Gbps). Early design changes based on accurate simulations can be indispensable and worthy investments for interconnect realization. Likewise, use of an accurate electromagnetic (EM) model is highly desirable during the design and implementation stage of high-speed interconnects. To achieve good SI, the designer must not only understand the system in which the connectors will be deployed, but also perform SI analysis of the RF board along with the connectors.

The Hybrid Approach
Over the years, various 3D interconnect simulation techniques have emerged to improve the integrated circuit density and operation speed of multilayer, very large, high-speed board integration designs. However, these techniques often lead to impedance discontinuities that induce SI/power integrity and electromagnetic interference effects when the RF board and connectors are simulated separately.

One way to address this challenge is with hybrid EM simulation. Essentially, with this approach, the connectors (or other 3D components) are integrated with the RF board and simulated together using planar and 3D EM simulation along with a transient solver. The planar simulation is based on a Method of Moment (MoM) solver, while the 3D-EM simulation relies on a Finite Element Method (FEM) solver.

To better understand how this hybrid approach works, consider the design and analysis of a serial ATA (SATA) to Universal Serial Bus (USB) data transfer module. Signals originating from the SATA connector go through two pairs of differential lines to a data transfer chip package. From the chip package, signals go to the USB connector through two pairs of differential lines routed on two different layers. The connectors, chip packages and printed circuit boards form electrical paths on which to conduct the SI analysis. Full-wave numerical analysis of the 3D high-speed and high-density interconnects is used for channel characterization to reduce the crosstalk, reflection and power-distribution noise problems that can cause false signal switching. In such applications, the main cause of impedance discontinuities and crosstalk is the area where the connector is attached to the RF board differential traces. To obtain accurate answers and avoid error-prone, time-consuming measurements, the SI of the complete integrated system must be taken into consideration.

Design and Simulation
Figure 1 illustrates the complete process for modeling the SATA to USB data transfer module. For the purposes of this discussion, the Advanced Design System (ADS) and EMPro software simulation tools were used to characterize the high-speed interconnects, including two connectors and the RF board.

Figure 1. The design flow used to model the SATA to USB data transfer module using ADS and EMPro, a 3D electromagnetic solver with both time- and frequency-domain based EM solvers.

In the first phase of the design process, two high-speed connectors (SATA and USB-3) are designed and simulated using EMPro. From this analysis, important factors from a SI point of view (e.g., impedance matching, reflection, attenuation, impedance mismatch, propagating delay, crosstalk, and alignment shapes of connectors) are analyzed. In order to minimize impedance effects, the connector contact geometry is designed to keep the impedance profile as flat as possible. If the contact spacing is insufficient to reduce crosstalk effect, shielding is applied.

Once designed, the connectors are imported into ADS as a library component. A multilayer SATA to USB-3 data transfer RF board with differential line traces connecting to a chip is then modeled and simulated in ADS layout using a planar EM MoM solver. Next, the SATA and USB connectors are integrated with the RF board module and the complete system simulated using the FEM solver in ADS layout. Finally, post layout SI analyses are carried out using a transient solver to validate waveform quality, timing and crosstalk.

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