Apply memory BIST to external DRAMs

-October 02, 2013

3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional, single-die embedded SRAM implementations. Gaining access to a DRAM requires predefined customized memory operations. EDA tools must make this definition step as simple as possible, while ensuring it can be reused across designs and over time. We also see that traditional test algorithms are less efficient on DRAMs, so they must be reconsidered in a 3D-IC context.

Comparing SRAMs and DRAMs
For testing SRAMs, EDA flows can automatically detect embedded memories and assign each instance to a specific BIST controller. This assignment depends on the chip architecture and includes user-defined parameters such as test time, power consumption limits, etc. A BIST engine typically tests many SRAMs in parallel through a simple interface (e.g., multiplexors).

To test external DRAMs used in 3D-ICs, the situation is, however, quite different. It often requires a new IP block, called the PHY (physical interface), which sits between the core logic and the memory. This PHY is reasonably complex and may also contain its own embedded I/O. A single BIST controller is then dedicated to test that specific PHY.

Defining memory operations: SRAM versus DRAM
Embedded SRAMs are easier to interface to than DRAMs. For example, to perform an operation known as a "read-modify-write" (RMW) on an SRAM, you perform a "read" on the first clock cycle followed by a "write" on the second clock cycle, as shown in Figure 1. Since SRAMs have distinct in-and-out busses (D and Q, respectively in Figure 1), no data collision occurs. A single RMW operation requires only two memory clock cycles to execute on a SRAM.

Figure 1. One read-modify-write (RMW) operation for an SRAM.

Another key feature of SRAMs is that they truly are "random access" memories because a test algorithm can access any valid memory location without constraints or conditions from previous tries.

In contrast, external DRAMs have more complex waveforms. They rely on pipelined architectures and generally use a bi-directional data bus. Consider the Wide I/O DRAM waveform in Figure 2. Based on JEDEC Standard #JESD229 waveforms, a single RMW operation would require 10 clock cycles to complete.

Figure 2. A Wide I/O DRAM waveform with a read latency RL=3 and write latency WL=1.

To mitigate latency effects, Wide I/O DRAMs actually access two or four consecutive locations per read or write command. This configurable feature is also known as the "burst mode" or "burst length" (BL). Assuming BL=2, an RMW operation thus requires an average of five clock cycles per memory location.

DRAMs also require PRE (precharge) and ACT (activate) commands on row changes. That is, the current row must first be closed with PRE before any other row can be opened within the same bank via ACT. The DRAM may also need periodic REF (refresh) commands, to ensure data is properly retained in its memory array. Alas, there are so many things to do and so little (test) time.

A flexible memory BIST system must let users provide simple waveforms for all these basic DRAM commands; it must then invoke them whenever appropriate while applying a test algorithm.

Efficiency of classical test algorithms
It should be noted that popular "March" test sequences typically rely on RMW operations described above. This isn’t surprising, as they were mostly developed to test SRAMs. For example, the syntax for a MarchC test algorithm is shown below. Its four main test phases are all performed as RMW (remember: 0 means "regular pattern," 1 means "inverted pattern."

On external DRAMs, the bus-turnaround cycles during RMW operations negatively impact test time. Additionally, an algorithm incrementing "row-fast" (i.e., rows before columns) will require more ACT and PRE commands, adding more overhead compared to the same algorithm that only increments "column-fast" (i.e., columns before rows). Three new DRAM-specific algorithms were developed to take advantage of burst mode and column-fast accesses, and for minimizing ACT/PRE command usage as much as possible. These algorithms rely on back-to-back read (or write) sequences rather than RMW operations. With the new algorithms, data bus utilization gets much closer to an ideal 100% and test time shrinks proportionally. The new algorithms are:
  1. SAFAU (Stuck-At Faults and Address Uniqueness): Ensures no memory array cell is stuck-at 0 or 1 and that all locations are uniquely accessed. Performed using pseudorandom data generator (PRDG), each phase using exactly the same initial seed. Test length: 4N.

  2. AT (Access Transistor): Detects excessive leakage in access transistors. Data inversion is applied on a per-row basis only. Test length: 8N.

  3. Coupling: Detects coupling between adjacent bitlines. Algorithm uses the pseudorandom data generator (PRDG) and is repeated at least L times using different seeds. Test length: Varies based on S (cell neighborhood size, from 1 to 4) and target FC% (fault coverage). The description in Figure 3 counts as 2 iterations because the first half is also re-run in the opposite direction. 

Figure 3. Fault coverage by number of times the coupling algorithm is repeated.

For example, a 99.99% coupling-fault coverage can be achieved between any cell and its closest neighbor (i.e., S=1) if the coupling algorithm is repeated at least 13 times. Given the algorithm shown above already performs two iterations, you could repeat it 7 times (i.e., a total of 14 executions).

Memory BIST implementations traditionally used on SRAMs can also be applied to DRAMs; however the read/write operations need to be redefined based on the actual PHY interface (or IOs) used in the design. EDA tools have to be flexible enough to support such operations. New algorithms to improve the testing of external DRAMS in a 3D IC context help keep test times to a minimum. These optimized algorithms address similar faults as their SRAM-based counterparts but provide a cost-effective solution for testing 3D ICs.

Also see
BIST grouping optimization for large-scale embedded memory design
BIST does support Serdes test
Dev Kits Need BIST, Too

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