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Tips & Tricks: JESD204B simplifies multi-chip synchronization

Thomas Neu, Texas Instruments -November 02, 2012

The use of multiple receive antennas to improve system performance has been employed for many years. In areas like wireless infrastructure, for example, a 2x2 or 4x4 MIMO architecture improves receiver sensitivity, coverage and/or increases data bandwidth and channel capacity. Other applications such as phased array radars exploit the phase information across multiple receivers allowing them to identify very small targets in cluttered environments with better resolution.

However, multi-chip synchronization in sampled systems has been anything but simple. For phased-array radars or MIMO radios, for example, it is crucial that samples from multiple receivers are aligned exactly with each other. Even a single clock cycle misalignment cannot be tolerated. Synchronization of multiple receivers requires timing calibration, careful routing and a detailed timing analysis to ensure that the propagation delay across different analog-to-digital converters (ADCs) does not result in channel-to-channel skew that is greater than one clock cycle.

Parallel interface

ADCs with a parallel digital interface provide a data bus together with an interface clock to latch in the data at the receiving device. When the sampling rate is slow enough, one common clock can be used to latch in data from multiple ADCs into the FPGA or ASIC, and still meet the setup and hold times across channels. However, as data rates increase, each data converter requires its own interface clock inside the receiving device, which increases cost and design complexity.

The challenge is that the clock input-to-output propagation delay of each ADC also contains a variable component. So the different data converter interface clocks can have different delays and the phase differences need to be absorbed with a FIFO inside the receiver. Since the parallel data interface doesn’t provide any type of indication for a specific sample, the use of a FIFO introduces uncertainty which may not be tolerable.

 

JESD204B Interface

The JESD204B interface solves all these issues and enables an easy and cost-effective way to synchronize and process multiple receivers.

Since the clock is embedded in the data stream, the JESD204B interface eliminates the need to match the trace length across the digital bus interface in order to maximize the setup and hold time window. The serialization of the output data stream drastically reduces board space and layout. The higher interface bit rate enables each data converter to use fewer IOs on the processor, enabling higher channel density and a lower cost system. A high-speed dual-channel 16-bit ADC with parallel DDR LVDS interface, for example, uses 17 differential pairs (16 data and one clock pairs) while using the JESD204B as with the ADS42JB69 (a dual, 16-bit 250 MSPS ADC), it can be reduced to just six differential pairs (four data and one SYNC).

 

The JESD204B standard also provides a simple method to synchronize multiple data converter ICs. For example, using the SYSREF signal in subclass 1, the internal local multi-frame clock (LMFCs) reference clock in each device across the system (ADC, DAC, FPGA, and so on) are aligned.

The ADC output data is mapped into frames where the frame boundaries are based on the LMFC. In other words, the relationship between each sample to the ADC internal reference clock is embedded in the output data stream. In that way, samples from different ADCs can easily be aligned as long as the SYNC signal is released to each data converter within the same LMFC cycle. The timing skew between JESD204B lanes across the same or different ADCs is absorbed with the elastic buffer inside the receiving device.

In order for the deterministic latency to work properly, the device clocks and SYSREF signals still need to be matched in length across all devices so that the LMFCs are aligned to the same sampling instant in time. Clock jitter cleaners supporting subclass 1, such as the LMK04828, also provide options to add different amounts of delay to individual outputs to compensate for different trace lengths.

Summary

Increasing bandwidth and performance requirements strengthen the need for multi-channel receiver arrays. The JESD204B interface promises an easy way to synchronize multiple receivers.


See related information:  TI device pair supports JEDEC JESD204B


About the Author

Thomas Neu is a systems engineer for TI’s high-speed data converters group where he provides applications support. Thomas received his MSEE from Johns Hopkins University, Baltimore, Maryland. He can be reached at ti_tneu@list.ti.com.

 

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