The circuit in Fig 1 is a digital latch that is resettable only after the condition that set the latch clears. A set input (active low) permanently latches the output (active low). A reset input (active high) resets the output to a logic high.

Unlike the 74279 set-reset latch, you can drive the set and reset lines low simultaneously. A 74279's output is unpredictable and unstable when you drive both its set and reset lines low simultaneously. In contrast, this circuit's output remains in its present state.

The circuit operates asynchronously and can handle both the set and reset inputs' changing state simultaneously. Applications include any circuit requiring a latch that will not reset until reaching a "safe" condition. A safe condition occurs when the set line has gone low and the reset line goes high. EDN BBS /DI_SIG #1413 contains an extensive writeup of this Design Idea's derivation.