The voltage-sorting circuit in Fig 1 continuously finds the maximum of eight input voltages and the corresponding binary address with the aid of two analog multiplexers, IC₁ and IC₂. The circuit compares each input sequentially with the current maximum voltage and updates the maximum voltage and address when it finds a new maximum. IC₂ and IC₃ act as storage elements. IC₄ ensures that latching can't occur at the beginning or the end of a given address, thereby preventing an incorrect address from being latched at an address transition. The sorter can also find the minimum of its input if you swap the CMP01 comparator's input.

The analog multiplexers, which typically have combined switching and settling times of 0.5 to 1.5 µsec, determine the minimum sorting time of this circuit. Overall sorting time is limited to about 1 µsec multiplied by the number of inputs. Given this constraint, you need to determine the desired overall sorting time and set the clock frequency accordingly. If V_MAX is used elsewhere, you should buffer it to avoid a voltage drop across the analog multiplexer's on resistance.

You can expand this eight-input sorter to 16 inputs without increasing the chip count by simply using two 16:1 analog multiplexers instead of two 8:1 multiplexers. This circuit already includes the next counter bit and D flip-flop required for the fourth address bit. You can further double the number of inputs to 32 by using three chips to form two 32:1 analog multiplexers.