Instead of resorting to full-blown frequency counters, the simple circuit in Fig 1 uses four ICs to rapidly compare the frequency of two pulse trains. The circuit produces a binary 0 if f₁ is greater than f₂ and a binary 1 if f₁ is less than f₂. The circuit exploits the fact that inevitably two consecutive leading edges of the higher frequency pulse train will follow each other in time without an intervening leading edge from the other pulse train. The circuit uses two pairs of flip-flops, IC₂ and IC₃, as 2-bit binary counters. A dual monostable multivibrator, IC₁, marks the leading edges of the input pulses by producing spikes of approximately 100 nsec in duration. The circuit couples each stream of spikes to the clock input of one counter and to the reset input of the other.

When one counter's clock receives two consecutive spikes without the arrival of an intervening reset pulse, the high-order bit of that counter goes high. Then, a latch formed by two NOR gates of IC₄ sets or resets depending on which of the two pulse trains has the higher frequency. If f₁ is greater than f₂, the latch resets to 0; if fis less than f₂, the latch sets to 1. The latch holds it state until there is a change in the relative magnitudes of the two frequencies.

For frequencies f₁ and f₂, the maximum response time of the circuit is given by the following

At 1 kHz and for f₁ and f₂ within 1% of each other, the circuit responds within 100 msec. One important note: The circuit is designed to handle asynchronous pulse trains, and it won't work if f₁ and f₂ are synchronous integral multiples of each other.