You can double the speed of a standard pseudonoise (PN) generator by using additional exclusive-OR gates and a fast 2:1 multiplexer. A PN generator built with an n-stage feedback shift register gives a maximal-length sequence of 2^N-1 bits. The upper limit of the PN-generator clock depends on the device logic family. For example, a PN generator built with 74LS74 flip-flops and a 74LS86 exclusive-OR gate has a top speed of 16 to 18 MHz. Fig 1's circuit doubles this speed by implementing a phase difference of half the sequence length. The multiplexer then combines and outputs this phase difference at double the rate of the original circuit.

Fig 1a shows a seven-stage PN generator built with flip-flops and one exclusive-OR gate. The outputs of FF₆ and FF₇ are modulo-2. The exclusive-OR gate adds and feeds back the outputs to FF₁ to obtain a maximal-length sequence. Fig 1b shows the reconfigured generator that produces two sequences at the outputs of FF₆ and FF₇ with a 64-bit difference between them. The multiplexer can combine these sequences to produce a 32-MHz output because the sequences can be as fast as 16 MHz. The general procedure for the connection, for any register length N with taps specified by its characteristic equation, is as follows:

1. Cascade odd and even flip-flops separately. This circuit cascades FF₁, FF₃, FF₅, and FF₇ and FF₂, FF₄, and FF₆ separately.
2. Apply the exclusive-OR sum of the original taps to D₂ instead of D₁. In Fig 1b, XOR₁ adds Q₆ and Q₇ and applies the result to D₂.
3. Use a second exclusive-OR gate to add the taps from one stage ahead of the original circuit. XOR₂ adds Q₅ and Q₆ and applies the result to D₁.
4. Multiplex outputs Q_N and Q_N-1, which are Q₆ and Q₇ in this example. (DI #1640)