| Figure 2 |
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| The organization of a 31-bit loadable counter in this CPLD shows that 36 inputs are adequate for the 32 signals that the least significant 15 bits and carry register require. |
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| Figure 2 |
|
| The organization of a 31-bit loadable counter in this CPLD shows that 36 inputs are adequate for the 32 signals that the least significant 15 bits and carry register require. |
back |