Fitting a large, loadable counter into a complex PLD (CPLD) while operating at the device's maximum frequency requires a few tricks. Fig 1 shows a 40-bit, loadable counter with a terminal-count output. The problem with fitting this design into a CPLD is that the design exceeds the usual number of logic-block inputs, which is 36 or fewer. Normally, for the most significant bit of a 40-bit counter, you must route 43 inputs into the logic block that registers: the 40 counter bits, the load control, the asynchronous-reset input, and that bit's data input for loading.
This design demonstrates how you can use token passing to fit large, loadable counters within a CPLD's available number of logic-block inputs. Registering these tokens allows the resulting design to operate at the CPLD's maximum frequency. These tricks are the keys to the successful implementation of a large, loadable counter in a CPLD.
Fig 2 shows how you can fit the counter into a 64-macrocell CPLD, the Flash370 CY7C373, while operating at full frequency. To ensure that the number of logic-block inputs is no more than 36, the design divides the counter into three groups. Two tokens in logic block A and one token in logic block B pass the necessary information regarding the state of the respective counter groups among counter groups. You must register the tokens for the resulting design to operate at the device's maximum frequency.
C1, C2, and CE operate as follows. C1 loads a 1 when the 14 counter bits in block A are all 1s. This setting of C1 can happen during a load operation or when the counter increments during normal counting. A C1 of 1 indicates that the 15 counter bits in block B need to increment on the next clock. Similarly, C2 loads a 1 when the 15 counter bits in block B are all 1s. The AND of C1 and C2 increments the enable for the 11 counter bits in block C. CE sets to a 1 when the 14 counter bits in block A are loaded with the HEX value of "3FFE." The states of CE, C2, and the 11 counter bits in block C determine when the terminal-count output, TC, becomes active.
We coded the design in VHDL. We compiled, synthesized, and targeted the design to the 64-macrocell CY7C373 using the Warp3 software-development system. The simulation shows that the TC output is active as desired when all 40 counter bits are 1. The TC output then changes to a 0 as the counter properly increments from all 1s to all 0s on the next clock. (DI #1702)
