Design Ideas: October 12, 1995
The Xilinx 4000 Series FPGA library contains a D-type flip-flop with either asynchronous preset or clear, but not both. The circuit in Fig 1 provides both functions, thereby eliminating the need to use discrete 74X74 ICs. The circuit consists of a set flip-flops, two reset flip-flops, a 4:1 multiplexer (of which you use only two channels), and a few logic gates. If either PR or CLR go low, the Q output of U4 switches high, regardless of the levels of CK or D. With S0 high and S1 low, the only input that multiplexer U7 accepts is Q from U5.
If PR goes low, U5-Q clocks to a high state; therefore, the output of U7 goes high. Similarly, CLR low resets U5-Q to a low state, and U7's output goes low. With both PR and CLR high, the first rising edge of CK sets U4-Q low, and thereby selects channel 0 in multiplexer U7. Depending on the state of U6-D when the clock arrived, the output of U6 can pass through U7 to the output. To prevent output glitches, you should ensure that the nets from U5-Q and U6-Q are slightly faster than from U4-Q. As with a discrete 74X74, you should avoid simultaneously setting PR and CLR low. If both these lines are low and CLR goes high, the output remains low. (DI#1777)