Design Ideas: April 11, 1996
A low-going input pulse on the load-input pin transfers the 8-bit parallel inputs into the shift register. Subsequently, the bits shift out at the appearance of a high-going pulse on the clock-input pin. The serial-input pin on the shift register connects to 5V, but you could also use it to cascade multiple shift registers. The TX and RTX signals drive comparators IC2A, IC2B, and associated components. The TX and RTS signals from the RS-232C line generate the load and clock signals for the shift register. The outputs of the LM324 slew rather slowly. The 74HC14 Schmitt-trigger buffers in IC3 square up the waveshape of the load and clock signals to the shift registers.
Comparator IC2C translates the serial output of the shift register to RS-232C levels. The CTS input of the RS-232C line reads this output signal. Diodes D1 through D6 and capacitors C1 and C2 generate the ±VCC supplies for the comparators. A 78L05 regulator generates 5V from the +VCC line for IC1 and IC3.
Figure 2 shows how the PC reads the switch matrix through the RS-232C port. The signals shown are those that appear at the shift-register pins. The clock pulses have a 2-msec width and 5-msec period.
Listing 1 gives a sample program that controls the switch matrix. (DI #1850)