Design Ideas: August 1, 1996

The reset and µP-controlled watchdog circuit in Figure 1 a makes good use of some unused inverter gates in IC₁. The design is extremely simple. The circuit is a continuously running oscillator with programmable high- and low-level pulse widths that have additional intervention-control input from the µP. Because the circuit is a continuous running oscillator, the circuit generates reset pulses at regular intervals. By sending high-level control pulses to the reset circuit at regular intervals, the µP retains control by stopping the reset pulse from occurring more than once. When the µP fails to send a control pulse within the allowed time, the watchdog-reset pulse automatically resets the µP. The circuit also generates an inverted reset using a second inverter gate, IC_1B, for low-active reset-signal requirements.

When power goes to V_CC, the reset output also goes high (Figure 1b). The reset time (RES) is programmable from 0.01 to 1 msec by adjusting R₂. Thereafter, the reset signal goes to a low level (TPRG). R₁ sets the duration of TPRG from 0.1 msec to 1 sec. A running program must be complete within the allowable TPRG period, and the µP must issue a high-level control pulse to extend the watchdog duration by the amount of CEPRG. Otherwise, the system faces a forced watchdog reset. In a trouble-free running system, the duration of CEPRG keeps increasing. If the program hangs up, then the watchdog reset for the duration of WRES becomes active and the system starts from the beginning. (DI #1900)