Design Ideas

Asynchronous circuit divides frequency by 1.5

Rolf Fielder, Ferrari Electronic GmbH, Teltow, Germany

In some designes, you need to provide a number of phase-related clocks to various components. In most cases, you generate the needed clocks by dividing a master clock by a power of two (synchronous division). However, sometimes, it is desireable to divide a frequency by an odd or even fractional divisor. In these cases, no synchronous method exists without generating a higher frequency master clock. Figure 1 shows the block diagram of an asynchronous clock divider that provides division by a factor of 1.5. By using this circuit and divid-by-two circuits, you can design clock dividers that provide the following divisors: N=1.5^k·2¹, where k and 1 are 0, 1, 2...

The circuit needs a master clock and a 90° phase-shifted master clock to operate properly. If the phase-shift is not exactly 90°, then the divided clock output has a duty cycle that's not exactly 1-to-1. Figure 2

shows simulation results (events-driven simulation) for the clock divider circuit. This simulation does not take the propogation delays of the gates into consideration. However, for the circuit to operate properly, it is important to balance the propogation delays of the clock and data lines of the latches. Listing 1 gives a GAL16V8 implementation of the divider circuit.

because of the internal construction of a GAL's product-term matrix, the propogation delays of all the critical paths match closely. The GAL implements the 90° phase shifter (by using a propogation delay) as well, entailing one external feedback connection. The clock-jitter performance and the duty cycle of the output signal depend on the performance of the 90° phase shifter. (DI #1934